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    2.
    发明专利
    未知

    公开(公告)号：DE60133021D1

    公开(公告)日：2008-04-10

    申请号：DE60133021

    申请日：2001-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： POLIZZI SALVATORE ,  PERRONI MAURIZIO

    IPC: G11C16/26 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32

    Abstract: A memory device includes a standard memory core, an input buffer receiving an external clock signal and producing an internal clock signal, an output path of data read from the standard memory core comprising a state machine receiving the internal clock signal for controlling the data stream coupled to the output of the standard memory through a first internal data bus, and an output buffer coupled to the output of the state machine through a second internal bus and comprising an output stage enabled by the state machine for producing the read data on an output bus. The memory device of the invention outputs the read data in a time starting from the rising edge of the external clock that is shorter than that of other known devices, because the output buffer has an array of master-slave pairs of flip-flops synchronized by respective timing signals derived from the internal clock signal, said array receiving data from the state machine through the second internal bus and providing the data to be output to the output stage of the buffer enabled by the state machine. A logic circuit generates timing signals for the master-slaves flip-flops, respectively as logic NAND and logic AND of the internal clock signal and of an enabling signal of the output stage of the buffer generated by the state machine. Moreover, the memory device comprises a circuit, synchronized by the internal clock signal, that introduces a delay of the enabling signal of the output stage of the buffer equivalent to a period of the internal clock signal.

    3.
    发明专利
    未知

    公开(公告)号：ITVA20020016A1

    公开(公告)日：2003-08-21

    申请号：ITVA20020016

    申请日：2002-02-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： POLIZZI SALVATORE ,  POLI SALVATORE ,  SCHILLACI PAOLINO

    IPC: G11C16/22

    Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

    5.
    发明专利
    未知

    公开(公告)号：ITVA20020012A1

    公开(公告)日：2003-08-08

    申请号：ITVA20020012

    申请日：2002-02-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PERRONI MAURIZIO ,  POLIZZI SALVATORE

    IPC: G11C7/10

    Abstract: A memory device includes an internal address bus, and first and second internal data busses. A memory receives from the internal address bus an address of memory data to be read, and transfers read memory data in blocks of N bits to the first internal data bus. An address storing circuit is coupled to the internal address bus for storing the address of the memory data to be read. An array of latches is coupled to the first internal data bus for storing the read memory data received therefrom. The array of latches includes two banks of latches. Each bank has N latches and is controlled independently from the other bank by respective commands, and each bank stores bits present on the first internal data bus upon receiving the respective commands. The second internal data bus is also connected to the array of latches. A state machine is connected to the array of latches for providing the respective commands for control thereof, and the state machine alternates the respective commands for commanding a consecutive reading of the blocks of N bits.

    6.
    发明专利
    未知

    公开(公告)号：ITVA20020016D0

    公开(公告)日：2002-02-21

    申请号：ITVA20020016

    申请日：2002-02-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： POLIZZI SALVATORE ,  POLI SALVATORE ,  SCHILLACI PAOLINO

    IPC: G11C16/22

    Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

    9.
    发明专利
    未知

    公开(公告)号：DE60214868D1

    公开(公告)日：2006-11-02

    申请号：DE60214868

    申请日：2002-12-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  GIAMBARTINO ANTONIO ,  LA MALFA ANTONINO ,  POLIZZI SALVATORE

    IPC: G11C16/10 ,  G11C16/12

    Abstract: The invention relates to a circuit architecture and a method for performing a page programming in non volatile memory electronic devices equipped with a memory cell matrix (3) and an SPI serial communication interface (2), as well as circuit portions associated to the cell matrix (3) and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank (5) is provided to store and draw data during the page programming in the pseudo-serial mode through said interface (2). Data latching is performed one bit at a time and the following data retrieval occurs instead with at least two bytes at a time.

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