AMPLIFICATION STEP PROTECTIVE CIRCUIT

    公开(公告)号:JPH07273563A

    公开(公告)日:1995-10-20

    申请号:JP32798494

    申请日:1994-12-28

    Abstract: PURPOSE: To obtain the amplification state protecting circuit which is reduced in the total number of circuit elements, specially, sense circuits and therefore improved in the reliability of protection and decreased in the integration area of the circuit. CONSTITUTION: This circuit is provided with a circuit switching means G which is piloted by a logic OR gate F by a monostable M and generates a turn-on command signal with predetermined continuation duration in case of an abnormal operating conditions. After a sense circuit B which senses an abnormal state at a start or in the normal operation enables an AND gate H, a turn-off signal is sent through the OR gate. The signal of the AND gate arrives as a confirmation signal through an OR logic gate C from a window comparator A coupled with an amplification stage start member, a monostable flip-flop, and the output terminal of the AND gate H.

    3.
    发明专利
    未知

    公开(公告)号:DE69326771T2

    公开(公告)日:2000-03-02

    申请号:DE69326771

    申请日:1993-12-07

    Abstract: An output power stage composed of a pair of transistors driven in phase opposition and wherein the pull-up transistor is a PNP bipolar transistor and the push-down transistor is an n-channel FET has an outstandingly improved power handling capability per semiconductor area occupied, coupled with a large output voltage swing, without requiring the use of externally connected discrete boot-strap components. The "hybrid" output stage is fully complementary and the current-driven, bipolar, pull-up transistor may be driven through an auxiliary stage composed of a field effect transistor for substantially eliminating output power requisites of a signal amplification stage.

    5.
    发明专利
    未知

    公开(公告)号:DE69326771D1

    公开(公告)日:1999-11-18

    申请号:DE69326771

    申请日:1993-12-07

    Abstract: An output power stage composed of a pair of transistors driven in phase opposition and wherein the pull-up transistor is a PNP bipolar transistor and the push-down transistor is an n-channel FET has an outstandingly improved power handling capability per semiconductor area occupied, coupled with a large output voltage swing, without requiring the use of externally connected discrete boot-strap components. The "hybrid" output stage is fully complementary and the current-driven, bipolar, pull-up transistor may be driven through an auxiliary stage composed of a field effect transistor for substantially eliminating output power requisites of a signal amplification stage.

    6.
    发明专利
    未知

    公开(公告)号:DE69320974T2

    公开(公告)日:1999-02-04

    申请号:DE69320974

    申请日:1993-12-31

    Abstract: Circuit for protection of an amplifier stage comprising circuit switching means (G) for turn-off of the stage and piloted through a logic gate OR (F) by a monostable (M), which generates upon arise of abnormal operating conditions turn-off command signals having a predetermined duration. A sensing circuit (B) upon persistence of abnormal conditions at start-up or during normal operation also sends turn-off signals through the logic gate OR (F) after enablement through a gate AND (H). The signals of any enablement at the logic gate AND arrive through a logic gate OR (C) from a window comparator (A) coupled with stage start-up members, from the monostable, and from the output of said logic gate AND (H) as a confirmation signal.

    7.
    发明专利
    未知

    公开(公告)号:DE69320974D1

    公开(公告)日:1998-10-15

    申请号:DE69320974

    申请日:1993-12-31

    Abstract: Circuit for protection of an amplifier stage comprising circuit switching means (G) for turn-off of the stage and piloted through a logic gate OR (F) by a monostable (M), which generates upon arise of abnormal operating conditions turn-off command signals having a predetermined duration. A sensing circuit (B) upon persistence of abnormal conditions at start-up or during normal operation also sends turn-off signals through the logic gate OR (F) after enablement through a gate AND (H). The signals of any enablement at the logic gate AND arrive through a logic gate OR (C) from a window comparator (A) coupled with stage start-up members, from the monostable, and from the output of said logic gate AND (H) as a confirmation signal.

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