公开(公告)号：JP2001169383A

公开(公告)日：2001-06-22

申请号：JP2000314791

申请日：2000-10-16

Applicant: ST MICROELECTRONICS SRL

Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

Abstract: PROBLEM TO BE SOLVED: To provide an audio amplifier where occurrence of an unrecoverable damage to a speaker can be avoided. SOLUTION: A detection interval or phase is established by applying a timing pulse with a frequency to an input of the detection circuit of this invention. The detection circuit detects a rising edge of the timing pulse to set a bistable circuit. A signal on an output node of an amplifier channel is compared with a window denoting a permissible value. After the initialization set, the bistable circuit is reset on the basis of production of a level of an output signal in the window denoting the permissible value. When the bistable circuit cannot be reset before the end of the detection phase, the detection circuit informs a user about the presence of an excessive offset.

公开(公告)号：DE60317806T2

公开(公告)日：2008-10-30

申请号：DE60317806

申请日：2003-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： CHELLI FABIO ,  BRAMBILLA DAVIDE

IPC: H03F3/68 ,  H03F1/02 ,  H03F1/32 ,  H03F3/30 ,  H03F3/45

Abstract: A method of preventing abrupt voltage changes at the outputs of a pair of amplifiers and a common mode control circuit of a pair of amplifiers that reduce EMI and increased distortions occur when the correlation between the signals that are fed to the four channels of the audio system diminishes has been found. This result is attained by properly generating for each amplifier a reference potential as a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration. This method is implemented in a common mode control circuit for a pair of amplifiers self-configuring in a bridge configuration for driving a first load and in a single-ended mode of operation of one of the amplifiers for driving the first load, in function of the level of a differential input signal, comprising for at least one of the pair of amplifiers a common mode feedback differential amplifier, a storage capacitor connected between any one of the two inputs of the feedback amplifier and a node at a reference potential, by providing the common mode control circuit of means for generating this reference potential.

公开(公告)号：DE69432637D1

公开(公告)日：2003-06-12

申请号：DE69432637

申请日：1994-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  CAPODIVACCA GIOVANNI ,  STEFANI FABRIZIO

IPC: G01R31/00 ,  G01R31/316

公开(公告)号：DE69528958D1

公开(公告)日：2003-01-09

申请号：DE69528958

申请日：1995-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  FERRARI PAOLO

IPC: H01L21/8222 ,  H01L27/06 ,  H01L29/861 ,  H01L27/00 ,  H01L27/02

Abstract: A monolithic output stage which is self-protected against the occurrence of incidental latch-up phenomena and integrated in a portion of a semiconductor material chip which is isolated by a peripheral barrier structure linked electrically to a terminal (Vcc), specifically a supply terminal being applied thereto a constant voltage (+Vcc), has the barrier structure coupled to the terminal (Vcc) through a forward biased diode (D1) from the terminal (Vcc). The integrated barrier structure is formed within a region (21'') having a first type of conductivity, and comprises a heavily doped well (29) having the first type of conductivity and a substantially annular shape and contacting a large surface of the chip (22). This structure is characterized in that, in at least one portion thereof close to contact regions (S) for connection to said terminal (Vcc), the barrier well (29) is split into first and second heavily doped concentrical regions (29' and 29'') having the first type of conductivity. The barrier structure further comprises, located at said portion, an intermediate region (30) which is less heavily doped and also has the first type of conductivity, and a surface region (31) with a second type of conductivity located within said intermediate region. The invention preferably involves a power output stage including a vertical PNP transistor isolated by said barrier well.

公开(公告)号：ITVA980026A1

公开(公告)日：2000-06-16

申请号：ITVA980026

申请日：1998-12-16

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  CAPODIVACCA GIOVANNI

IPC: H03F3/30

Abstract: A circuit for ensuring a complete saturation of both operational amplifiers of a single-input bridge amplifier is provided. A voltage divider is connected between the inverting inputs of the two amplifiers and a saturation current signal is injected on the intermediate node of the voltage divider. Such a saturation current signal is obtained through dedicated sensing devices of the state of saturation reached by the transistors of the output stages of both amplifiers of the single-input bridge amplifier.

公开(公告)号：DE69533696D1

公开(公告)日：2004-12-02

申请号：DE69533696

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  NEBULONI DANIELA ,  ROSSI GIORGIO ,  LECCE SERGIO

IPC: G05F3/26 ,  H03F3/345

Abstract: A current generator circuit with controllable frequency response is of a type which comprises at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (Iout) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg. In accordance with the invention, the mirror circuit further comprises an impedance matching means (3) connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching means (3) has an adjustable output impedance, specifically lower in value than the value to be had without this means. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

公开(公告)号：DE69528958T2

公开(公告)日：2003-09-11

申请号：DE69528958

申请日：1995-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  FERRARI PAOLO

IPC: H01L21/8222 ,  H01L27/06 ,  H01L29/861 ,  H01L27/00 ,  H01L27/02

Abstract: A monolithic output stage which is self-protected against the occurrence of incidental latch-up phenomena and integrated in a portion of a semiconductor material chip which is isolated by a peripheral barrier structure linked electrically to a terminal (Vcc), specifically a supply terminal being applied thereto a constant voltage (+Vcc), has the barrier structure coupled to the terminal (Vcc) through a forward biased diode (D1) from the terminal (Vcc). The integrated barrier structure is formed within a region (21'') having a first type of conductivity, and comprises a heavily doped well (29) having the first type of conductivity and a substantially annular shape and contacting a large surface of the chip (22). This structure is characterized in that, in at least one portion thereof close to contact regions (S) for connection to said terminal (Vcc), the barrier well (29) is split into first and second heavily doped concentrical regions (29' and 29'') having the first type of conductivity. The barrier structure further comprises, located at said portion, an intermediate region (30) which is less heavily doped and also has the first type of conductivity, and a surface region (31) with a second type of conductivity located within said intermediate region. The invention preferably involves a power output stage including a vertical PNP transistor isolated by said barrier well.

公开(公告)号：DE69902889D1

公开(公告)日：2002-10-17

申请号：DE69902889

申请日：1999-06-15

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  CAPODIVACCA GIOVANNI ,  RANIERI DANILO

IPC: H03F1/52 ,  H03F3/30 ,  H03F3/50 ,  G05F1/569

公开(公告)号：IT1305651B1

公开(公告)日：2001-05-15

申请号：ITVA980027

申请日：1998-12-16

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  CAPODIVACCA GIOVANNI

IPC: H03F1/30

Abstract: The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.

公开(公告)号：IT1305650B1

公开(公告)日：2001-05-15

申请号：ITVA980026

申请日：1998-12-16

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  CAPODIVACCA GIOVANNI

IPC: H03F3/30

Abstract: A circuit for ensuring a complete saturation of both operational amplifiers of a single-input bridge amplifier is provided. A voltage divider is connected between the inverting inputs of the two amplifiers and a saturation current signal is injected on the intermediate node of the voltage divider. Such a saturation current signal is obtained through dedicated sensing devices of the state of saturation reached by the transistors of the output stages of both amplifiers of the single-input bridge amplifier.