公开(公告)号：JPH10335478A

公开(公告)日：1998-12-18

申请号：JP13185698

申请日：1998-05-14

Applicant: ST MICROELECTRONICS SRL

Inventor： STUCCHI ELENA ,  DAFFRA STEFANO ,  CEREDA MANLIO SERGIO

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/329 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/8605

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit without making a manufacturing process complex and without increasing the number of generated defects. SOLUTION: An insulation layer for constituting a polycrystal Si part that prescribes an opening for forming the gate electrode and the resistor of a MOSTr, a P ion injection 27 with a low amount of concentration for forming a pair of n-type conductive parts 19 and 20 at both sides of a gate thin line part (electrode) 14, and the injection mask of polycrystalline Si including an n-type conductive resistance part 21 due to an opening are formed. Then, a resist insulation layer is formed on an entire structure, an insulation layer is subjected to anisotropic etching so that the region of a substrate without Si mask can be exposed, and the residue of an insulation material remains along the edge part of the gate electrode. For compensating for the elimination of a surface layer from a resistance part due to etching, a dosage amount where the resistance part 21 becomes a scheduled resistance value are subjected to second ion implantation by energy without any substrate mask and without changing resistance values in source and drain of MOSTr.

公开(公告)号：JPH07201848A

公开(公告)日：1995-08-04

申请号：JP29764794

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  DAFFRA STEFANO ,  STUCCHI ELENA

IPC: H01L21/318 ,  H01L21/314 ,  H01L27/115

Abstract: PURPOSE: To reduce the extent of complexity of processes, to provide superior reliability, and to lower the cost of a device instituted by this method. CONSTITUTION: By an inactivating method which uses a silicon oxide nitride, a circuit structure is converted with a 1st layer 8 of at least a dielectric substance before its layer is formed, and a 2nd layer 9 of a dielectric substance is laminated on it. These layers 8 and 9 are thick enough to planarize the surface of the top part. Further, this is usable together with an inactivating method which features flattening by the formation of the same dielectric layer by a base shape and does not use oxide nitride 10.

公开(公告)号：DE69737947D1

公开(公告)日：2007-09-06

申请号：DE69737947

申请日：1997-05-20

Applicant: ST MICROELECTRONICS SRL

Inventor： STUCCHI ELENA ,  DAFFRA STEFANO ,  CEREDA MANLIO SERGIO

IPC: H01L21/00 ,  H01L27/04 ,  H01L21/02 ,  H01L21/329 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/8605

Abstract: The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips (14) for constituting the gate electrodes of the MOS transistors and portions (16) defining openings (17) for the formation of resistors, low-dose ionic implantation (18) through the implantation mask to form pairs of regions (19, 20) at the sides of the gate strips (14) and resistive regions (21) through the openings, the formation of an insulating layer (30) on the entire structure thus produced, and anisotropic etching of the insulating layer (30) so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask but leaving a residue (22) of insulating material along the edges of the gate strips (14). To compensate for the removal of a surface layer from the resistive regions due to the anisotropic etching, a second low-dose implantation is carried out without masking of the substrate, with a dose and an energy such as to produce a predetermined resistivity for the resistive regions (21) without altering the resistivities of the source and drain regions of the MOS transistors.