公开(公告)号：JPH10302479A

公开(公告)日：1998-11-13

申请号：JP8093998

申请日：1998-03-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BARONI ANDREA ,  RIMONDI DANILO ,  TALIERCIO MICHELE ,  TORELLI COSIMO

IPC: G11C11/41 ,  G11C7/14 ,  G11C11/413 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To reduce current consumption in the write mode by installing a dummy memory train roughly the same as the memory cell to monitor the switching time of the dummy memory and selecting the short time alone strictly required for the operation that the desired line to be programmed switches the memory cell to the desired state. SOLUTION: The device is provided with a memory cell 2, a dummy memory train DC(DMCD0-DMCn) roughly the same as the memory cell and plural gates RD1-RDn which transfer the selected output of the line decoder 3 to the lines. The pre-charge control means 4' pre-charges the dummy train DC to the first logic state when the line is not selected. The detecting means DET1 detects the state where the dummy train DC is discharged from the pre-charge potential to the programming potential by the programming means which makes the dummy train DC correspond to the second logic state contrary to the first one to enable plural gates RD1-RDn and disable them after transferring to the second logic state.

公开(公告)号：DE69723226D1

公开(公告)日：2003-08-07

申请号：DE69723226

申请日：1997-04-03

Applicant: ST MICROELECTRONICS SRL

Inventor： BARONI ANDREA ,  RIMONDI DANILO ,  TALIERCIO MICHELE ,  TORELLI COSIMO

IPC: G11C11/41 ,  G11C7/14 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00 ,  G11C11/409

Abstract: A memory device comprises an array (1) of memory cells (2,DMC0-DMCn) arranged in rows (R1-Rn) and columns (C1-Cm,DC), a plurality of gates (RD1-RDn) for transmitting respective selection outputs (RS1-RSn) of a row decoder (3) to respective rows (RS), a dummy column (DC) of dummy memory cells (DMC0-DMCn) substantially indentical to the memory cells, precharge means (P4,P5,P6,P7) for precharging the columns and the dummy column at a precharge potential (VDD) when no row is selected, and programming means (N7,N8,7) for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means (P3) for presetting the dummy memory cells in a first logic state when no row is selected; dummy column programming means (N9,N10) for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state; first detector means (DET1) for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of said gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from said first logic state to said second logic state.

公开(公告)号：DE60037248T2

公开(公告)日：2008-10-09

申请号：DE60037248

申请日：2000-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA ,  ATTI MASSIMO ,  PALUMBO ELISABETTA ,  TORELLI COSIMO

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

Abstract: A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

公开(公告)号：ITVA20070041A1

公开(公告)日：2008-10-12

申请号：ITVA20070041

申请日：2007-04-11

Applicant: ST MICROELECTRONICS SRL

Inventor： RIMONDI DANILO ,  SELVA CAROLINA ,  TORELLI COSIMO ,  ZAPPA RITA

公开(公告)号：ITVA20060081A1

公开(公告)日：2008-06-23

申请号：ITVA20060081

申请日：2006-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： RIMONDI DANILO ,  TORELLI COSIMO ,  ZAPPA RITA

公开(公告)号：DE60037248D1

公开(公告)日：2008-01-10

申请号：DE60037248

申请日：2000-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA ,  ATTI MASSIMO ,  PALUMBO ELISABETTA ,  TORELLI COSIMO

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

Abstract: A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.