公开(公告)号：JPH0690008A

公开(公告)日：1994-03-29

申请号：JP15141493

申请日：1993-05-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CLEMENTI CESARE ,  GHIDINI GABRIELLA ,  TOSI MARINA

IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: PURPOSE: To provide the device with less defects in the case, wherein it is required not only to decrease merely the width, depth, and the thickness of a layer and the like in the scale down of the device but also to hold the fundamental electric performance of an integrated structure and the O-N-O structure for this purpose is proposed. CONSTITUTION: The nitride surface layer of polysilicon is formed by treating the surface of a polysilicon layer 5 in nitrogen atmosphere at the temperature of 900 deg.C to 1,100 deg.C for 15 to 150 seconds. The nitride silicon layer is deposited on the surface. Under the temperature of 900 deg.C to 1,000 deg.C in the presence of water vapor, the silicon-nitride deposited layer is oxidized so as to have the thickness of 20 nm from the silicon-oxide insulating layer 5, and a plurality of layers 6 are formed.

公开(公告)号：DE60331629D1

公开(公告)日：2010-04-22

申请号：DE60331629

申请日：2003-01-15

Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

Inventor： PELLIZZER FABIO ,  BEZ ROBERTO ,  TOSI MARINA

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/24

Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

公开(公告)号：DE60226839D1

公开(公告)日：2008-07-10

申请号：DE60226839

申请日：2002-02-20

Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

Inventor： BEZ ROBERTO ,  PELLIZZER FABIO ,  TOSI MARINA ,  ZONCA ROMINA

IPC: H01L45/00 ,  H01L27/24

公开(公告)号：DE69226358D1

公开(公告)日：1998-08-27

申请号：DE69226358

申请日：1992-05-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CLEMENTI CESARE ,  GHIDINI GABRIELLA ,  TOSI MARINA

IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28

Abstract: The use of an O-N-RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O-N-O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling down.