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    EPROM CELL PROVIDED WITH INTERPOLY-INSULATOR CAPABLE OF BEING EASILY SCALED DOWN AND ITS MANUFACTURE
    1.
    发明专利
    EPROM CELL PROVIDED WITH INTERPOLY-INSULATOR CAPABLE OF BEING EASILY SCALED DOWN AND ITS MANUFACTURE 失效

    公开(公告)号：JPH0690008A

    公开(公告)日：1994-03-29

    申请号：JP15141493

    申请日：1993-05-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CLEMENTI CESARE ,  GHIDINI GABRIELLA ,  TOSI MARINA

    IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

    Abstract: PURPOSE: To provide the device with less defects in the case, wherein it is required not only to decrease merely the width, depth, and the thickness of a layer and the like in the scale down of the device but also to hold the fundamental electric performance of an integrated structure and the O-N-O structure for this purpose is proposed. CONSTITUTION: The nitride surface layer of polysilicon is formed by treating the surface of a polysilicon layer 5 in nitrogen atmosphere at the temperature of 900 deg.C to 1,100 deg.C for 15 to 150 seconds. The nitride silicon layer is deposited on the surface. Under the temperature of 900 deg.C to 1,000 deg.C in the presence of water vapor, the silicon-nitride deposited layer is oxidized so as to have the thickness of 20 nm from the silicon-oxide insulating layer 5, and a plurality of layers 6 are formed.

    INTEGRATED DEVICE AND ITS PREPARATION
    2.
    发明专利
    INTEGRATED DEVICE AND ITS PREPARATION 失效

    公开(公告)号：JPH06224377A

    公开(公告)日：1994-08-12

    申请号：JP24002693

    申请日：1993-09-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CRISENZA GIUSEPPE ,  CLEMENTI CESARE

    IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To provide an integrated device in which an LDD structure is partially overlapped on a gate region on a low-doped region. CONSTITUTION: An integrated device is provided with a first polycrystalline silicon layer 12, having a first length in a first direction, an insulating layer 13, and a gate region 18 consisting of a second polycrystalline silicon layer and a third polycrystalline silicon layer on a substrate 2. Also, this device is provided with first substrate regions 37 and 38 and second substrate regions 26 and 29 buried in the substrate under the first polycrystalline silicon layer 12. Moreover, the insulating layer 13 provides an insulating part with a prescribed width in a second direction vertical to a first direction, and the gate region is electrically and directly brought into contact with the first polycrystalline silicon layer in at least one part extended from the insulating part to the second direction of the gate region.

    4.
    发明专利
    未知

    公开(公告)号：ITTO980516A1

    公开(公告)日：1999-12-13

    申请号：ITTO980516

    申请日：1998-06-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZATELLI NICOLA ,  CREMONESI CARLO ,  CLEMENTI CESARE ,  PIO FEDERICO

    IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

    Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

    6.
    发明专利
    未知

    公开(公告)号：DE69528970D1

    公开(公告)日：2003-01-09

    申请号：DE69528970

    申请日：1995-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CLEMENTI CESARE ,  GHIDINI GABRIELLA ,  RIVA CARLO

    IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

    Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for: removal of said layers from the peripheral zones (R2) of the matrix; deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2). To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.

    7.
    发明专利
    未知

    公开(公告)号：DE69232311D1

    公开(公告)日：2002-01-31

    申请号：DE69232311

    申请日：1992-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CRISENZA GIUSEPPE ,  CLEMENTI CESARE

    IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L21/28

    Abstract: A method comprising the steps of depositing a first (12) and second (17) polysilicon layer, separated by an oxide layer (13); selectively etching the second polysilicon layer (17) to form first gate regions (18); forming first substrate regions (26, 29) in the substrate (2) and laterally in relation to the first gate regions; selectively etching the first polysilicon layer (12) to form second gate regions of a length greater than the first gate regions (18); and forming, in the substrate, laterally in relation to the second gate regions (12) and partially overlapping the first substrate regions (26, 29), second substrate regions (37, 38) of a higher doping level than the first substrate regions (26, 29).

    10.
    发明专利
    未知

    公开(公告)号：DE69227772T2

    公开(公告)日：1999-06-24

    申请号：DE69227772

    申请日：1992-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CRISENZA GIUSEPPE ,  CLEMENTI CESARE

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/41

    Abstract: A method comprising the steps of depositing a first (12) and second (17) polysilicon layer, separated by an oxide layer (13); selectively etching the second polysilicon layer (17) to form first gate regions (18); forming first substrate regions (26, 29) in the substrate (2) and laterally in relation to the first gate regions; selectively etching the first polysilicon layer (12) to form second gate regions of a length greater than the first gate regions (18); and forming in the substrate, laterally in relation to the second gate regions (12) and partially overlapping the first substrate regions (26, 29), second substrate regions (37, 38) of a higher doping level than the first substrate regions (26, 29).

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