公开(公告)号：ITUB20154179A1

公开(公告)日：2017-04-01

申请号：ITUB20154179

申请日：2015-10-01

Applicant: ST MICROELECTRONICS SRL

Inventor： CARDU ROBERTO ,  PICCA MASSIMILIANO ,  TREVISAN LORENZO ,  PORTA CRISTIAN

IPC: H02M3/335 ,  H02M3/337

Abstract: A method for driving a resonant converter comprising a primary switching circuit having at least a primary winding and a primary full-bridge switching stage (M1, M2, M3, M4), and an inductor (Lres) in series with the primary winding, a secondary resonant circuit having a secondary winding magnetically coupled to the primary winding, a resonance capacitor (Cres) electrically connected in parallel to the secondary winding, a secondary rectification stage electrically connected in parallel to the resonance capacitor (Cres), which has a first switch (M6) and a second switch (M5), each connected between a respective terminal of the resonance capacitor (Cres) and ground. Moreover provided is a driving module, configured for receiving at input an enabling signal (START) and the voltage (Phase) measured across the switch (M*) of the secondary side, the driving module being configured for generating a control signal (SW) for controlling the switches of the secondary side (M*). The method comprises executing cyclically the following sequence of operations: - turning on low-side switches (M1, M3) of said primary switching stage and both switches (M5, M6) of said secondary rectification stage and turning off high-side switches (M2, M4) of the primary switching stage; - after a fixed time, turning off the low-side switch (M3) and turning on the high-side switch (M4) of the primary switching stage; - waiting for a rising edge (RE) of said enabling signal (START); - waiting for the condition of zero current (ZCD) flowing in the switches of the secondary side (M5, M6, M*) to be satisfied; - turning off the first switch (M*, M6) of the secondary side by sending the control signal (SW) to the low level (0 V) after a variable delay (Dzcd(n)) with respect to the rising edge of the enabling signal (START), and keeping the second switch (M5) of the secondary side on; - waiting for the condition of zero voltage across the first switch (M*, M6) of the secondary side to be satisfied; - switching back on the first switch (M*, M6) of the secondary side by sending the control signal (SW) to the high level when the voltage (Phase) measured across the first switch of the secondary side (M*, M6) drops below a variable threshold (Vthzvs); and executing the previous operations, reversing, with respect to one another, the roles of the high-side switches (M2, M4) and low-side switches (M1, M3) of the primary switching stage and reversing, with respect to one another, the roles of the first switch (M6) and second switch (M5) of the secondary rectification stage.

公开(公告)号：ITUB20154121A1

公开(公告)日：2017-04-01

申请号：ITUB20154121

申请日：2015-10-01

Applicant: ST MICROELECTRONICS SRL

Inventor： TREVISAN LORENZO ,  PICCA MASSIMILIANO ,  CARDU ROBERTO ,  PORTA CRISTIAN

IPC: H02M3/337 ,  H02M1/38

Abstract: A method for driving a resonant converter comprising a primary switching circuit having at least a primary winding and a primary full-bridge switching stage (M1, M2, M3, M4), configured for driving said primary winding, and a resonance inductor (Lres) in series with the primary winding, a secondary resonant circuit having a secondary winding magnetically coupled to the primary winding, a resonance capacitor (Cres) electrically connected in parallel to the secondary winding, a secondary rectification stage electrically connected in parallel to the resonance capacitor (Cres), and a driving module. The driving module is configured for receiving at input a signal (PHX, PHY) representing the voltage measured across an upper switching half-bridge (M1, M2) or a lower switching half-bridge (M3, M4), detecting the presence of a negative voltage in the signal (PHX, PHY) representing the voltage measured across said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4), and at each cycle anticipating (Tshift nom) the control signal (PWMY_OUT, PWMX_OUT) for control of the switches of the lower switching half-bridge (M3, M4) or upper switching half-bridge (M1, M2), that is to be activated at the next switching cycle, by a shift time (Tshift) that is reduced (´tshift) at each cycle until (Tshift_targ) the condition of absence of negative voltage in the signal (PHX, PHY) representing the voltage measured across said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4) is satisfied.