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公开(公告)号：JP2001057097A
公开(公告)日：2001-02-27
申请号：JP2000227650
申请日：2000-07-27
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , KHOURI OSAMA , SACCO ANDREA , PICCA MASSIMILIANO
Abstract: PROBLEM TO BE SOLVED: To obtain a single power voltage type non-volatile storage device having a hierarchical column decoder in which the bias time of a word line at the level of staircase voltage can be shortened. SOLUTION: This storage device 10 has a memory cell array 2 having structure of a form provided with global word lines 4 and local word lines 6, a global column decoding means 8 for addressing the global word lines 4, a local column decoding means 12 for addressing the local word lines 6, a global power supply means 22 for supplying power to the global column decoding means 8, and a local power supply means 24 for supplying power to a local column decoding means 12.
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公开(公告)号：ITUB20154179A1
公开(公告)日：2017-04-01
申请号：ITUB20154179
申请日：2015-10-01
Applicant: ST MICROELECTRONICS SRL
Inventor： CARDU ROBERTO , PICCA MASSIMILIANO , TREVISAN LORENZO , PORTA CRISTIAN
Abstract: A method for driving a resonant converter comprising a primary switching circuit having at least a primary winding and a primary full-bridge switching stage (M1, M2, M3, M4), and an inductor (Lres) in series with the primary winding, a secondary resonant circuit having a secondary winding magnetically coupled to the primary winding, a resonance capacitor (Cres) electrically connected in parallel to the secondary winding, a secondary rectification stage electrically connected in parallel to the resonance capacitor (Cres), which has a first switch (M6) and a second switch (M5), each connected between a respective terminal of the resonance capacitor (Cres) and ground. Moreover provided is a driving module, configured for receiving at input an enabling signal (START) and the voltage (Phase) measured across the switch (M*) of the secondary side, the driving module being configured for generating a control signal (SW) for controlling the switches of the secondary side (M*). The method comprises executing cyclically the following sequence of operations: - turning on low-side switches (M1, M3) of said primary switching stage and both switches (M5, M6) of said secondary rectification stage and turning off high-side switches (M2, M4) of the primary switching stage; - after a fixed time, turning off the low-side switch (M3) and turning on the high-side switch (M4) of the primary switching stage; - waiting for a rising edge (RE) of said enabling signal (START); - waiting for the condition of zero current (ZCD) flowing in the switches of the secondary side (M5, M6, M*) to be satisfied; - turning off the first switch (M*, M6) of the secondary side by sending the control signal (SW) to the low level (0 V) after a variable delay (Dzcd(n)) with respect to the rising edge of the enabling signal (START), and keeping the second switch (M5) of the secondary side on; - waiting for the condition of zero voltage across the first switch (M*, M6) of the secondary side to be satisfied; - switching back on the first switch (M*, M6) of the secondary side by sending the control signal (SW) to the high level when the voltage (Phase) measured across the first switch of the secondary side (M*, M6) drops below a variable threshold (Vthzvs); and executing the previous operations, reversing, with respect to one another, the roles of the high-side switches (M2, M4) and low-side switches (M1, M3) of the primary switching stage and reversing, with respect to one another, the roles of the first switch (M6) and second switch (M5) of the secondary rectification stage.
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公开(公告)号：ITUB20154121A1
公开(公告)日：2017-04-01
申请号：ITUB20154121
申请日：2015-10-01
Applicant: ST MICROELECTRONICS SRL
Inventor： TREVISAN LORENZO , PICCA MASSIMILIANO , CARDU ROBERTO , PORTA CRISTIAN
Abstract: A method for driving a resonant converter comprising a primary switching circuit having at least a primary winding and a primary full-bridge switching stage (M1, M2, M3, M4), configured for driving said primary winding, and a resonance inductor (Lres) in series with the primary winding, a secondary resonant circuit having a secondary winding magnetically coupled to the primary winding, a resonance capacitor (Cres) electrically connected in parallel to the secondary winding, a secondary rectification stage electrically connected in parallel to the resonance capacitor (Cres), and a driving module. The driving module is configured for receiving at input a signal (PHX, PHY) representing the voltage measured across an upper switching half-bridge (M1, M2) or a lower switching half-bridge (M3, M4), detecting the presence of a negative voltage in the signal (PHX, PHY) representing the voltage measured across said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4), and at each cycle anticipating (Tshift nom) the control signal (PWMY_OUT, PWMX_OUT) for control of the switches of the lower switching half-bridge (M3, M4) or upper switching half-bridge (M1, M2), that is to be activated at the next switching cycle, by a shift time (Tshift) that is reduced (´tshift) at each cycle until (Tshift_targ) the condition of absence of negative voltage in the signal (PHX, PHY) representing the voltage measured across said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4) is satisfied.
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公开(公告)号：DE602004002947D1
公开(公告)日：2006-12-07
申请号：DE602004002947
申请日：2004-07-14
Applicant: ST MICROELECTRONICS SRL
Inventor： PICCA MASSIMILIANO , ZANARDI STEFANO
IPC: G11C29/00
Abstract: An electrically programmable memory ( 100 ) including: an array ( 105 ) of a plurality of memory cells ( 210 ) arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks (225_1 - 225 K) and each memory block including a plurality of memory pages; means for receiving (106,I/O,112,115) an address corresponding to a respective memory block; selecting means ( 120,125r,195,125r,130,155 ) for selecting the addressed memory block; and means for detecting (REG_1 - REG_K,135,145,147) a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers (REG_1 - REG_K), each regis (AR, RED ADD) of the failure of the respective memory block; and means for reading ( 135,145,147 ) the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block ( RED_1 - RED_M ) of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.
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公开(公告)号：ITMI20061272A1
公开(公告)日：2008-01-01
申请号：ITMI20061272
申请日：2006-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： AMATO STEFANO , MANNINO FRANCESCO , PICCA MASSIMILIANO , SCAPIN MIRKO
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Patent Agency Ranking
公开(公告)号：DE602004002947T2
公开(公告)日：2007-06-28
申请号：DE602004002947
申请日：2004-07-14
Applicant: ST MICROELECTRONICS SRL
Inventor： PICCA MASSIMILIANO , ZANARDI STEFANO
IPC: G11C29/00
Abstract: An electrically programmable memory ( 100 ) including: an array ( 105 ) of a plurality of memory cells ( 210 ) arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks (225_1 - 225 K) and each memory block including a plurality of memory pages; means for receiving (106,I/O,112,115) an address corresponding to a respective memory block; selecting means ( 120,125r,195,125r,130,155 ) for selecting the addressed memory block; and means for detecting (REG_1 - REG_K,135,145,147) a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers (REG_1 - REG_K), each regis (AR, RED ADD) of the failure of the respective memory block; and means for reading ( 135,145,147 ) the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block ( RED_1 - RED_M ) of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.
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公开(公告)号：IT1316870B1
公开(公告)日：2003-05-12
申请号：ITMI20000687
申请日：2000-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , COMMODARO STEFANO , PICCA MASSIMILIANO , MONGELLI PATRIZIA
IPC: G11C29/56
Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.
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公开(公告)号：DE69927364D1
公开(公告)日：2005-10-27
申请号：DE69927364
申请日：1999-07-28
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , KHOURI OSAMA , SACCO ANDREA , PICCA MASSIMILIANO
Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).
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公开(公告)号：IT1319937B1
公开(公告)日：2003-11-12
申请号：ITTO20000207
申请日：2000-03-03
Applicant: ST MICROELECTRONICS SRL
Inventor： ZANARDI STEFANO , BRANCHETTI MAURIZIO , MULATTI JACOPO , PICCA MASSIMILIANO
IPC: G01R31/317 , G11C29/46
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公开(公告)号：ITTO20010529A1
公开(公告)日：2002-12-02
申请号：ITTO20010529
申请日：2001-06-01
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , ZANARDI STEFANO , PICCA MASSIMILIANO , RAVASIO ROBERTO
Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.
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