公开(公告)号：JP2001291049A

公开(公告)日：2001-10-19

申请号：JP2001052695

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  CAZZANIGA MARCO ,  VENCA ALESSANDRO

IPC: G06G7/16 ,  G06G7/163 ,  H03D7/14

Abstract: PROBLEM TO BE SOLVED: To provide a low supply voltage analog multiplier for supplying an extremely low supply voltage and improving the linearity of input while keeping a sufficient speed by performing the cascade connection of plural stages. SOLUTION: A pair of differential cells 10 and 11 are provided and the respective differential cells are provided with a pair of bipolar transistors 2, 3, 6 and 7 whose emitters are connected to each other. The first transistors 2 and 6 of the respective cells 10 and 11 receive input signals IN+ and IN- at the base terminals and the collector terminals are connected to a first reference voltage Vcc through bias members 4 and 8. The second transistors 3 and 7 of the respective cells are diode constitution and the cells are mutually connected at a common node A corresponding to the base terminals of the second transistors 3 and 7 of the respective pairs.

公开(公告)号：DE602005013715D1

公开(公告)日：2009-05-20

申请号：DE602005013715

申请日：2005-04-14

Applicant: ST MICROELECTRONICS SRL ,  ST MICROELECTRONICS INC

Inventor： VENCA ALESSANDRO ,  ALINI ROBERTO ,  POSAT BARIS

IPC: G11B5/02 ,  G05F3/26 ,  G11B5/00 ,  G11B5/09 ,  H02M3/07

公开(公告)号：ITMI20000391D0

公开(公告)日：2000-02-29

申请号：ITMI20000391

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  VENCA ALESSANDRO ,  CAZZANIGA MARCO

IPC: G06G7/16 ,  G06G7/163 ,  H03D7/14

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

公开(公告)号：IT1316688B1

公开(公告)日：2003-04-24

申请号：ITMI20000391

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： VENCA ALESSANDRO ,  PISATI VALERIO ,  CAZZANIGA MARCO

IPC: G06G7/16 ,  G06G7/163 ,  H03D7/14

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

公开(公告)号：ITMI20000391A1

公开(公告)日：2001-08-29

申请号：ITMI20000391

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  VENCA ALESSANDRO ,  CAZZANIGA MARCO

IPC: G06G7/16 ,  G06G7/163 ,  H03D7/14

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.