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公开(公告)号：JP2001291049A
公开(公告)日：2001-10-19
申请号：JP2001052695
申请日：2001-02-27
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , CAZZANIGA MARCO , VENCA ALESSANDRO
Abstract: PROBLEM TO BE SOLVED: To provide a low supply voltage analog multiplier for supplying an extremely low supply voltage and improving the linearity of input while keeping a sufficient speed by performing the cascade connection of plural stages. SOLUTION: A pair of differential cells 10 and 11 are provided and the respective differential cells are provided with a pair of bipolar transistors 2, 3, 6 and 7 whose emitters are connected to each other. The first transistors 2 and 6 of the respective cells 10 and 11 receive input signals IN+ and IN- at the base terminals and the collector terminals are connected to a first reference voltage Vcc through bias members 4 and 8. The second transistors 3 and 7 of the respective cells are diode constitution and the cells are mutually connected at a common node A corresponding to the base terminals of the second transistors 3 and 7 of the respective pairs.
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2.发明专利
公开(公告)号：JP2001285027A
公开(公告)日：2001-10-12
申请号：JP2001040561
申请日：2001-02-16
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: PROBLEM TO BE SOLVED: To obtain a feedforward type circuit structure, having programmable zero which composes a time-continual filter, a delaychain, etc. SOLUTION: A couple of amplification cells (14, 15) are connected to each other at a node A and connected between a 1st signal (Vin) input IN of a 1st cell 14 and an output terminal U of a 2nd cell 15, and each cell is equipped with a couple of transistors (10, 2; 6, 7) which have a common conduction terminal and other conduction terminals coupled with a 1st voltage reference Vcc through respective bias members. Furthermore, a node X of the 1st cell 14 is connected to the output terminal U and a transistor 8 has a control terminal connected to a node X of the 1st cell 14, a 1st conduction terminal connected to an output terminal U, and a 2nd conduction terminal coupled with a 2nd voltage reference GND through a capacitor Cc. The transistor 8 is equipped with a circuit leg 13.
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公开(公告)号：JP2001274657A
公开(公告)日：2001-10-05
申请号：JP2001031150
申请日：2001-02-07
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ROSSI AUGUSTO , BETTI GIORGIO , CAZZANIGA MARCO
Abstract: PROBLEM TO BE SOLVED: To provide an FIR filter design that has a structure and a functional feature suitable for processing a signal whose spectrum is not known in advance and executes Hilbert transform so as to eliminate limitations and overcome defects of the design of a conventional technology. SOLUTION: This invention relates to a time continuous FIR(finite impulse response) filter that executes the Hilbert transform. The filter is provided with a delay cell connected in cascade between an input terminal and an output terminal of the filter and with a programmable time delay(Td) for a programmable filter cell having fixed filter coefficients (c0,..., cn). Furthermore, this invention also relates to a filtering method to use the structure of the Hilbert FIR filter to process a signal produced by reading data from a magnetic storage medium adopting the vertical recording.
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公开(公告)号：DE69631772D1
公开(公告)日：2004-04-08
申请号：DE69631772
申请日：1996-12-04
Applicant: ST MICROELECTRONICS SRL
Inventor： REZZI FRANCESCO , CASTELLO RINALDO , CAZZANIGA MARCO , BIETTI IVAN
IPC: H03H11/04
Abstract: The invention relates to an elementary biquadratic cell for programmable time-continous analog filters, which is placed between a first supply voltage reference (Vdd) and a second voltage reference (GND) and is of a type having at least one pair of input terminals (I31,I31') and first (O31,O31') and second (O32,O32') pairs of output terminals, and having a pair of half-cells (31,31'), which half-cells are structurally identical with each other and each comprised of at least a first transistor (T31,T31') placed between the first (Vdd) and the second (GND) voltage reference and having a base terminal connected to a respective one of the input terminals (I31,I31'). Each half-cell (31,31') further comprises second (T32,T32') and third (T33,T33') transistors placed between the first (Vdd) and second (GND) voltage references, the second transistor (T32,T32') having a base terminal connected to the first output terminal (O31,O31') of the first pair of output terminals and a collector terminal connected to the second output terminal (O32,O32') of the second pair of output terminals, and the third transistor (T33,T33') having an emitter terminal connected to the first output terminal (O31,O31') of the first pair of output terminals ad a base terminal connected to the second output terminal (O32',O32) of the second pair of output terminals of the other half-cell.
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公开(公告)号：ITMI20000393D0
公开(公告)日：2000-02-29
申请号：ITMI20000393
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： CASTELLO RINALDO , PORTALURI SALVATORE , PISATI VALERIO , CAZZANIGA MARCO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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Patent Agency Ranking
公开(公告)号：DE60032727D1
公开(公告)日：2007-02-15
申请号：DE60032727
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ROSSI AUGUSTO , BETTI GIORGIO , CAZZANIGA MARCO
Abstract: The invention relates to a time-continous FIR (Finite Impulse Response) filter whereby a Hilbert transform can be implemented. The filter comprises a cascade of delay cells connected between an input terminal of the filter and an output terminal; constant filter coefficients (cO,...,cn) and a programmable time delay (Td) of the programmable filter cells are provided. The invention also relates to a filtering method effective to enable use of this Hilbert FIR filter structure for processing signals originated by the reading of data from magnetic storage media which employ perpendicular recording.
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公开(公告)号：DE60103691D1
公开(公告)日：2004-07-15
申请号：DE60103691
申请日：2001-01-15
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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公开(公告)号：ITMI20000391D0
公开(公告)日：2000-02-29
申请号：ITMI20000391
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , VENCA ALESSANDRO , CAZZANIGA MARCO
Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.
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公开(公告)号：IT1316690B1
公开(公告)日：2003-04-24
申请号：ITMI20000393
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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公开(公告)号：IT1316688B1
公开(公告)日：2003-04-24
申请号：ITMI20000391
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： VENCA ALESSANDRO , PISATI VALERIO , CAZZANIGA MARCO
Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.
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