中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.024 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE60307606D1

    公开(公告)日：2006-09-28

    申请号：DE60307606

    申请日：2003-06-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SCHIPPERS STEFAN ,  VIMERCATI DANIELE ,  BOLANDRINA EFREM

    IPC: G11C7/14 ,  G11C16/28

    Abstract: A method is described for generating a reference current (Iref) for sense amplifiers (11) connected to cells (12) of a memory matrix (1) comprising the steps of: generating a first reference current analogue signal (REF) through a reference cell (14). Advantageously according to the invention, the method further comprises the steps of: performing an Analog-to-Digital conversion of the first analogue signal (REF) into a reference current digital signal (REF_BITÄ3:0Ü); sending the digital signal (REF_BITÄ3:0Ü) on a connection line (43) to the sense amplifiers (11); and performing a Digital-to-Analog conversion of the digital signal (REF_BITÄ3:0Ü) into a second reference current analogue signal (REF1) to be applied as reference current (Iref) to the sense amplifiers (11). The invention also relates to a reference current generator effective to implement this method.

    2.
    发明专利
    未知

    公开(公告)号：DE60317768D1

    公开(公告)日：2008-01-10

    申请号：DE60317768

    申请日：2003-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIMERCATI DANIELE

    IPC: G11C11/56

    Abstract: A reading method for a nonvolatile memory device (1), wherein the gate terminals of the array memory cell (3) and of the reference memory cell (7) are supplied with a same reading voltage (VREAD) having a ramp-like pattern, so as to modify their current-conduction states in successive times, and the contents of the array memory cell (3) are determined on the basis of the modification order of the current-conduction states of the array memory cell (3) and of the reference memory cell (7).

    3.
    发明专利
    未知

    公开(公告)号：DE602006009476D1

    公开(公告)日：2009-11-12

    申请号：DE602006009476

    申请日：2006-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIMERCATI DANIELE ,  BOLANDRINA EFREM ,  GAROFALO PIERGUIDO

    IPC: G11C5/14 ,  G05F3/20

    Abstract: A method is described for generating a controlled current by means of a Band Gap circuitry (10) comprising the steps of: - supplying on a Band Gap node (BGAP), a Band Gap voltage signal that is stable in temperature and power supply; - driving a controlled current generator (2) by means of this Band Gap voltage signal; and mirroring the controlled current signal generated on an output terminal of the Band Gap circuitry; Advantageously according to the invention, the method further comprises, after the driving step, a step of locally suppressing a disturb of the controlled current signal generated by the controlled current generator (2) by means of a disturb suppression circuit (11) connected to said Band Gap node acting on said Band Gap voltage signal. A disturb suppression circuit and a Band Gap circuitry for the generation of a controlled current signal are also described.

    4.
    发明专利
    未知

    公开(公告)号：DE60329899D1

    公开(公告)日：2009-12-17

    申请号：DE60329899

    申请日：2003-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIMERCATI DANIELE ,  SCHIPPERS STEFAN ,  MIRICHIGNI GRAZIANO ,  VILLA CORRADO

    IPC: G11C16/08 ,  G11C8/08

    Abstract: A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

    7.
    发明专利
    未知

    公开(公告)号：DE60317768T2

    公开(公告)日：2008-11-27

    申请号：DE60317768

    申请日：2003-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIMERCATI DANIELE

    IPC: G11C11/56

    Abstract: A reading method for a nonvolatile memory device (1), wherein the gate terminals of the array memory cell (3) and of the reference memory cell (7) are supplied with a same reading voltage (VREAD) having a ramp-like pattern, so as to modify their current-conduction states in successive times, and the contents of the array memory cell (3) are determined on the basis of the modification order of the current-conduction states of the array memory cell (3) and of the reference memory cell (7).

Patent Agency Ranking