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公开(公告)号：JP2002050187A
公开(公告)日：2002-02-15
申请号：JP2001207874
申请日：2001-07-09
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO
Abstract: PROBLEM TO BE SOLVED: To provide a method for changing threshold voltage of a non-volatile memory cells at high speed and the circuit configuration that optimizes the uses of a charge pump and the device reliability. SOLUTION: This method is a method for changing threshold voltage of plural non-volatile memory cells after erasure processing, for example, flash EEPROM memory cells (NOR-MX). This method is characterized in that it is provided with a step in which all column lines are connected to a voltage supply source (CH-P, V-REG) to optimize use of a voltage source for column bias while equalization of threshold voltage is performed at high speed, a step (V-SEN) in which supply voltage is monitored, and a step (V-GEN, R-REG) in which voltage being variable from the prescribed minimum value to the prescribed maximum value and its change rate is adjusted to the maximum possible value being compatible with a state, in which supply voltage of a column line is kept to the approximately fixed prescribed value, is supplied to all row lines.
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公开(公告)号：DE60328354D1
公开(公告)日：2009-08-27
申请号：DE60328354
申请日：2003-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO
IPC: G11C11/56
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公开(公告)号：DE602006007095D1
公开(公告)日：2009-07-16
申请号：DE602006007095
申请日：2006-02-06
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO , BELTRAMI SILVIA
IPC: G11C16/10
Abstract: A non-volatile memory device (100) is provided. Said memory device includes a matrix (105) of memory cells (110(i,j)) arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal; a plurality of bit lines (BLj) each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line; a plurality of first biasing lines (WLi) each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line; a plurality of second biasing lines (SLi) each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line; and means for programming (130b,130s,130w) at least one selected memory cell belonging to a selected row. The means for programming includes first biasing means (130w) for applying a programming voltage (Vpw) first biasing lines, and second biasing means (130s) for applying a program enabling voltage (GND) to a selected second biasing line associated with the selected row, each memory cell being programmed only when receiving both the programming voltage and the program enabling voltage.
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公开(公告)号：ITMI20011232D0
公开(公告)日：2001-06-12
申请号：ITMI20011232
申请日：2001-06-12
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO
IPC: G11C16/34
Abstract: A method of re-programming an array of non-volatile memory cells after an erase operation is provided where a re-program operation is executed to restore a threshold voltage of the memory cells to a higher value than a depletion verify voltage value. The method may include identifying a first value of the depletion verify voltage, executing the re-program operation using the value of the depletion verify voltage, and verifying the array of re-programmed cells for reliability in a read mode. If the outcome of the verifying step is favorable, the re-program operation is terminated as successful. Otherwise, the value of the depletion verify voltage is modified, and the re-program operation is again executed using the modified value of the depletion verify voltage as adjusted for the actual operating conditions of the memory array.
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Patent Agency Ranking
公开(公告)号：DE602006016065D1
公开(公告)日：2010-09-23
申请号：DE602006016065
申请日：2006-03-10
Applicant: ST MICROELECTRONICS SRL , MILANO POLITECNICO
Inventor： VISCONTI ANGELO , BONANOMI MAURO , IELMINI DANIELE , SPINELLI ALESSANDRO
IPC: G11C16/10
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公开(公告)号：DE69905237T2
公开(公告)日：2003-10-30
申请号：DE69905237
申请日：1999-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO
Abstract: The inventive concept on which the present invention is based, consists of implementing a method for correction of the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the present correction method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical basis other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary basis, to a basis n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a basis n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical basis used for the conversion. This makes it possible to reduce the number of multilevel memory cells used, and for specific values of m and n, the saving is such that the detection and correction of errors does not require multilevel memory cells in addition to the m/b multilevel memory cells which would be necessary for storing the m bits in the binary word.
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公开(公告)号：DE60312117D1
公开(公告)日：2007-04-12
申请号：DE60312117
申请日：2003-12-16
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO
Abstract: An error detection structure (115) is proposed for a multilevel memory device (100) including a plurality of memory cells (105) each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means (370-385) for detecting errors in the values of a selected block of memory cells; the structure further includes means (365) for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.
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公开(公告)号：DE69905237D1
公开(公告)日：2003-03-13
申请号：DE69905237
申请日：1999-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO
Abstract: The inventive concept on which the present invention is based, consists of implementing a method for correction of the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the present correction method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical basis other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary basis, to a basis n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a basis n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical basis used for the conversion. This makes it possible to reduce the number of multilevel memory cells used, and for specific values of m and n, the saving is such that the detection and correction of errors does not require multilevel memory cells in addition to the m/b multilevel memory cells which would be necessary for storing the m bits in the binary word.
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公开(公告)号：ITMI20011232A1
公开(公告)日：2002-12-12
申请号：ITMI20011232
申请日：2001-06-12
Applicant: ST MICROELECTRONICS SRL
Inventor： VISCONTI ANGELO
IPC: G11C16/34
Abstract: A method of re-programming an array of non-volatile memory cells after an erase operation is provided where a re-program operation is executed to restore a threshold voltage of the memory cells to a higher value than a depletion verify voltage value. The method may include identifying a first value of the depletion verify voltage, executing the re-program operation using the value of the depletion verify voltage, and verifying the array of re-programmed cells for reliability in a read mode. If the outcome of the verifying step is favorable, the re-program operation is terminated as successful. Otherwise, the value of the depletion verify voltage is modified, and the re-program operation is again executed using the modified value of the depletion verify voltage as adjusted for the actual operating conditions of the memory array.
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