公开(公告)号：JPH07106275A

公开(公告)日：1995-04-21

申请号：JP18026393

申请日：1993-07-21

Applicant: ST MICROELECTRONICS SRL

Inventor： ZACCHERINI CHIARA

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8244 ,  H01L27/11

Abstract: PURPOSE: To form an implantation region with a low risk for causing a channel phenomenon by implanting a first dopant species with a large atomic weight, making amorphous the polycrystalline silicon at a non-mask part, eliminating the mask, and implanting a second dopant species into the entire region on a semiconductor. CONSTITUTION: An ion is implanted into a specific region 8 of a polycrystalline silicon layer 7 on a field oxide 5. Then, the ion is implanted heavily using an N-type dopant seed 11 with a large atomic weight such as arsenic or phosphorus. When such a heavy implantation process is executed, the polycrystalline silicon layer 7 at a part that is located on a channel region 4 of the device 1 and is not protected by a photoresist 10 becomes amorphous. Then, the protection photoresit 10 is eliminated. After that, a P-type dopant such as boron is implanted with a medium or small amount of dosage.

公开(公告)号：DE69330986D1

公开(公告)日：2001-11-29

申请号：DE69330986

申请日：1993-07-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ZACCHERINI CHIARA

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8244 ,  H01L27/11

Abstract: A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor.

公开(公告)号：ITMI922003D0

公开(公告)日：1992-08-19

申请号：ITMI922003

申请日：1992-08-19

Applicant: ST MICROELECTRONICS SRL ,  SGS THOMSON MICROELECTRONICS

Inventor： ZACCHERINI CHIARA

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8244 ,  H01L27/11

Abstract: A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor.

公开(公告)号：DE69330986T2

公开(公告)日：2002-06-13

申请号：DE69330986

申请日：1993-07-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ZACCHERINI CHIARA

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8244 ,  H01L27/11

Abstract: A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor.

公开(公告)号：IT1256362B

公开(公告)日：1995-12-04

申请号：ITMI922003

申请日：1992-08-19

Applicant: ST MICROELECTRONICS SRL

Inventor： ZACCHERINI CHIARA

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8244 ,  H01L27/11 ,  H01L

Abstract: A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor.