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    Circuit for detecting leaky access switches in cmos imager pixels
    2.
    发明公开
    Circuit for detecting leaky access switches in cmos imager pixels 有权
    Schalungsanordnung zur Erkennung leckender Zugriffsschalter在CMOS-Bildaufnehmerpixels

    公开(公告)号：EP0915619A1

    公开(公告)日：1999-05-12

    申请号：EP98308774.3

    申请日：1998-10-27

    Applicant: STMicroelectronics, Inc.

    Inventor： Kramer, Alan H. ,  Rambaldi, Roberto ,  Tartagni, Marco

    IPC: H04N5/217 ,  H04N3/15

    CPC classification number: H04N5/367 ,  H04N5/374

    Abstract: Disclosed is a CMOS image sensor that includes circuitry for identifying defective pixels, particularly pixels having leaky access switches. The leaky access switches allow charge to escape from the pixel over a row or column line in a pixel array, thereby corrupting the outputs of an entire row or column of pixels. A disclosed test involves (a) electronically setting a defined charge in a selected pixel of the CMOS imager; (b) reading the output of the selected pixel; and (c) comparing the output of the selected pixel to an expected value based upon the defined charge set in the selected pixels. If the output significantly deviates from the expected value, then the selected pixel is identified as having a leaky access switch. Preferably, a newly fabricated sensor is first tested as described. If such leaky access switch is discovered, the imager is discarded without incurring further manufacturing cost. If, on the other hand, the imager is not found to contain a leaky access switch, it may packaged and then subjected to an optical test.

    Abstract translation: 公开了一种CMOS图像传感器，其包括用于识别缺陷像素的电路，特别是具有泄漏接入开关的像素。 泄漏的访问开关允许电荷从像素阵列中的行或列线上的像素逸出，从而破坏整个像素行或列的输出。 公开的测试涉及（a）在CMOS成像器的选定像素中电子地设定定义的电荷; （b）读取所选像素的输出; 以及（c）基于所选择的像素中设定的定义的电荷，将所选像素的输出与预期值进行比较。 如果输出显着偏离预期值，则所选择的像素被识别为具有泄漏接入开关。 优选地，如上所述首先测试新制造的传感器。 如果发现这样的泄漏接入交换机，则丢弃该成像器而不产生进一步的制造成本。 另一方面，如果没有发现成像器包含泄漏接入开关，则可以将其封装，然后进行光学测试。

    Pixel correction system and method for CMOS imagers
    4.
    发明公开
    Pixel correction system and method for CMOS imagers 有权
    System and Verfahren zur BildelementkorrekturfürCMOS-Bildsensoren

    公开(公告)号：EP0917358A1

    公开(公告)日：1999-05-19

    申请号：EP98308762.8

    申请日：1998-10-27

    Applicant: STMicroelectronics, Inc.

    Inventor： Rambaldi, Roberto ,  Tartagni, Marco ,  Kramer, Alan H.

    IPC: H04N5/217

    CPC classification number: H04N5/367 ,  H04N5/374

    Abstract: Disclosed is a fault tolerant CMOS image sensor that includes circuitry for identifying defective pixels and masking them during image generation. Masking may involve, in one example, replacing the output of a given pixel with an average of the output of surrounding non-faulty pixels. Thus, while image sensors may be fabricated with some number of faulty pixels, the images produced by such sensors will not have undesirable bright or dark spots. The disclosed sensor includes (a) one or more pixels (active or passive) capable of providing outputs indicative of a quantity of radiation to which each of the one or more pixels has been exposed; and (b) one or more circuit elements electrically coupled to the one or more pixels and configured to identify and correct faulty pixels in the CMOS imager. The one more pixels each include a photodiode diffusion formed in a well and a tap to power or ground also formed in the well. The disclosed sensor also identifies pixels that were initially acceptable but later became defective. The newly defective pixels so identified may then be masked to thereby increase the CMOS detector lifetime.

    Abstract translation: 公开了一种容错CMOS图像传感器，其包括用于识别缺陷像素并在图像生成期间对其进行掩蔽的电路。 在一个示例中，掩蔽可以涉及用周围的非故障像素的输出的平均值替换给定像素的输出。 因此，虽然图像传感器可以被制造成具有若干个有缺陷的像素，但由这种传感器产生的图像将不会有不期望的明亮或暗点。 所公开的传感器包括（a）能够提供指示一个或多个像素中的每一个已被暴露的辐射量的输出的一个或多个像素（有源或无源） 和（b）一个或多个电路元件，其电耦合到所述一个或多个像素并且被配置为识别和校正所述CMOS成像器中的有缺陷的像素。 每个像素中的每一个包括在阱中形成的光电二极管扩散器和也形成在阱中的电源或接地的接头。 所公开的传感器还识别最初可接受但后来变得有缺陷的像素。 然后可以掩蔽如此识别的新缺陷像素，从而增加CMOS检测器的寿命。

    Backside bus vias
    6.
    发明公开
    Backside bus vias 审中-公开
    KontaktlöcherfürRückseitenbus

    公开(公告)号：EP1073103A1

    公开(公告)日：2001-01-31

    申请号：EP00305710.6

    申请日：2000-07-06

    Applicant: STMicroelectronics, Inc.

    Inventor： Kramer, Alan H. ,  Thomas, Danielle A.

    IPC: H01L21/306 ,  H01L23/48 ,  H01L25/065

    CPC classification number: H01L23/544 ,  H01L21/76804 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2224/05599

    Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside.

    Abstract translation: 总线导体的金属抽头形成在一个有源层内，一个或多个金属化层中，位于总线通孔区域的基板的有源侧。 对准标记形成在相同的金属层中，在同一区域。 然后从基板的背面盲孔蚀刻槽，暴露金属丝锥和对准标记。 使用氧化物或氮化物硬掩模将槽蚀刻到具有显着倾斜的侧壁的衬底的背面中，允许金属在背面沉积和图案化。

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