公开(公告)号：US20140367828A1

公开(公告)日：2014-12-18

申请号：US14306934

申请日：2014-06-17

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Jean-Philippe Colonna ,  Sylvain Joblot ,  Thierry Mourier ,  Olivier Guiller

IPC: H01L49/02 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L28/40 ,  H01G2/103 ,  H01G4/236 ,  H01G4/35 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.

Abstract translation: 一种器件包括在第一侧上的衬底和集成电路互连。 电容器通过具有第一电极的基板，该第一电极具有电耦合到放置在基板的第二侧上的第一导电区域的第一接触面和与该互连件电耦合的第二电极。 透硅通孔穿过基板，其一端具有电耦合到位于基板的所述第二侧上的第二导电区的第一接触面，另一端电耦合到互连部分。 两个第一接触面位于同一平面内。

公开(公告)号：US09647625B2

公开(公告)日：2017-05-09

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02 ,  H03H9/02 ,  H03H3/04 ,  H03H9/00 ,  H03H9/17 ,  G02F1/1337 ,  G01N29/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

公开(公告)号：US11251053B2

公开(公告)日：2022-02-15

申请号：US16990556

申请日：2020-08-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Joel Schmitt ,  Bilel Saidi ,  Sylvain Joblot

IPC: H01L21/00 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/321 ,  H01L21/3215 ,  H01L23/528

Abstract: An electrode is included in a base substrate. A trench is produced in the base substrate. The trench is filled with an annealed amorphous material to form the electrode. The electrode is made of a crystallized material which includes particles that are implanted into a portion of the electrode that is located adjacent the front-face side of the base substrate.

公开(公告)号：US09224796B2

公开(公告)日：2015-12-29

申请号：US14306934

申请日：2014-06-17

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Jean-Philippe Colonna ,  Sylvain Joblot ,  Thierry Mourier ,  Olivier Guiller

IPC: H01L21/20 ,  H01L49/02 ,  H01L23/48 ,  H01L21/768 ,  H01L23/64

CPC classification number: H01L28/40 ,  H01G2/103 ,  H01G4/236 ,  H01G4/35 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.

Abstract translation: 一种器件包括在第一侧上的衬底和集成电路互连。 电容器通过具有第一电极的基板，该第一电极具有电耦合到放置在基板的第二侧上的第一导电区域的第一接触面和与该互连件电耦合的第二电极。 透硅通孔穿过基板，其一端具有电耦合到位于基板的所述第二侧上的第二导电区的第一接触面，另一端电耦合到互连部分。 两个第一接触面位于同一平面内。

公开(公告)号：US20140075726A1

公开(公告)日：2014-03-20

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract translation: 一种制造晶片的方法，其上形成有谐振器，每个谐振器包括在半导体衬底上方的一叠层，其从衬底表面依次包括：布拉格反射镜; 由具有与所有其它堆叠层相反的符号的声速的温度系数的材料制成的补偿层; 和压电谐振器，该方法包括以下连续步骤：a）沉积补偿层; 和b）由于沉积方法而减小补偿层的厚度不等式，使得该层在每个谐振器的电平上具有相同的厚度，优于2％以内，优选在1％以内。