Abstract:
The instant invention provides memory system incorporating shared redundant memories and shared redundant memory architecture. More particularly, the instant invention discloses a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories forming a single logical memory or various memories in close proximity on a SoC. The shared redundancy is achieved by adding a comparator to the redundant element for comparing between the faulty address and the system address and performing a memory operation based on the comparator output. As the redundant memory operations are performed in parallel to the memory structures, it results in reduced setup and hold time. Shared redundancy also results in reduced SoC area.
Abstract:
The present invention provides a built-in self-repairable memory. The invention repairs the faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses lesser number of fuses to actually make a perfect repair and thus result into a yield enhancement. The fuse data is stored in a compressed form and then decompressed at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).
Abstract:
The present invention relates to a method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.
Abstract:
The present invention provides a built-in self-repairable memory. The invention repairs the faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses lesser number of fuses to actually make a perfect repair and thus result into a yield enhancement. The fuse data is stored in a compressed form and then decompressed at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).