公开(公告)号：EP4134688A2

公开(公告)日：2023-02-15

申请号：EP22186502.5

申请日：2022-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  BENDOTTI, Valerio ,  FINAZZI, Luca ,  BAGNATI, Gaudenzia

IPC: G01R31/42 ,  H02M3/158 ,  H02M1/32

Abstract: A circuit, comprising: a high-side transistor pair (S 0H , HS) and a low-side transistor pair (S 0L , LS) having a common intermediate node (OUT S, OUT), wherein the high-side transistor pair (S 0H , HS) comprises a first transistor (HS) having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node (OUT_D) and the intermediate node (OUT_S, OUT) as well as a second transistor (S 0H ) having a current flowpath therethrough coupled to the control node of the first transistor (HS), wherein the low-side transistor pair (S 0L , LS) comprises a third transistor (LS) having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node (OUT, OUT_S) and the reference voltage node (PGND) as well as a fourth transistor (S 0L ) having a current flowpath therethrough coupled to the control node of the third transistor (LS). The circuit comprises testing circuitry (40; 50) comprising a test-mode node (TM) configured to receive a test-mode signal (V TM ), the testing circuitry (40; 50) configured to be coupled to at least one of the second transistor (S 0H ) in the high-side transistor pair (S 0H , HS) and of the fourth transistor (S 0L ) in the low-side transistor pair (S 0L , LS) to apply thereto the test-mode signal (V TM ) wherein the at least one of the high-side transistor pair (S 0H , HS) and the low-side transistor pair (S 0L , LS) is made selectively conductive or non-conductive based on the test-mode signal (V TM ).

公开(公告)号：EP4134688A3

公开(公告)日：2023-03-01

申请号：EP22186502.5

申请日：2022-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  BENDOTTI, Valerio ,  FINAZZI, Luca ,  BAGNATI, Gaudenzia

IPC: H02M3/158 ,  H02M1/32 ,  G01R31/42

Abstract: A circuit, comprising: a high-side transistor pair (S 0H , HS) and a low-side transistor pair (S 0L , LS) having a common intermediate node (OUT S, OUT), wherein the high-side transistor pair (S 0H , HS) comprises a first transistor (HS) having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node (OUT_D) and the intermediate node (OUT_S, OUT) as well as a second transistor (S 0H ) having a current flowpath therethrough coupled to the control node of the first transistor (HS), wherein the low-side transistor pair (S 0L , LS) comprises a third transistor (LS) having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node (OUT, OUT_S) and the reference voltage node (PGND) as well as a fourth transistor (S 0L ) having a current flowpath therethrough coupled to the control node of the third transistor (LS). The circuit comprises testing circuitry (40; 50) comprising a test-mode node (TM) configured to receive a test-mode signal (V TM ), the testing circuitry (40; 50) configured to be coupled to at least one of the second transistor (S 0H ) in the high-side transistor pair (S 0H , HS) and of the fourth transistor (S 0L ) in the low-side transistor pair (S 0L , LS) to apply thereto the test-mode signal (V TM ) wherein the at least one of the high-side transistor pair (S 0H , HS) and the low-side transistor pair (S 0L , LS) is made selectively conductive or non-conductive based on the test-mode signal (V TM ).