公开(公告)号：EP1378824A1

公开(公告)日：2004-01-07

申请号：EP02425436.9

申请日：2002-07-02

Applicant: STMicroelectronics S.r.l.

Inventor： Borneo, Antonio Maria ,  Rovati, Fabrizio Simone ,  Pau, Danilo Pietro

IPC: G06F9/38

CPC classification number: G06F9/3879 ,  G06F9/3853 ,  G06F9/3877

Abstract: Programs having a given instruction-set architecture (ISA) are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length (L1 respectively L2) executable on a first processor (VLIW 1 respectively VLIW 2). At least some of the instruction words of given length are converted (IIU) into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of:

splitting the instruction words into modified-instruction words; and
entering no-operation (nop) instructions in the modified-instruction words.

Abstract translation: 具有给定的指令集架构（ISA）的程序被执行的多处理器系统，其包括处理器上的多个，对于VLIW类型的实施例，每个所述处理器能够执行，在每个处理循环中，指令的respectivement最大数目 ， 该指令被编译为在第一处理器上给定长度（L1分别L2）可执行的指令字（VLIW 1分别VLIW 2）。 至少一些给定长度的指令字的转换（IIU）转换成在第二处理器上执行的修改的指令字。 反过来至少一个手术选择的组中的由...组成，所述修改包括的手术：将所述指令字写入改性指令字; 并进入经修改的指令字无操作（NOP）指令。

公开(公告)号：EP1416393A1

公开(公告)日：2004-05-06

申请号：EP02257603.7

申请日：2002-11-01

Applicant: STMicroelectronics, Ltd. ,  STMicroelectronics S.r.l.

Inventor： Homewood, Mark Owen ,  Borneo, Antonio Maria

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system comprises a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; a FIFO connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the said data can be supplied from the FIFO to the stream register unit; and a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.

Abstract translation: 通过通信信道（8）连接到流注册单元（5）的先​​进先出（FIFO）存储器（16）从外设接收数据。 数据通过通道从存储器提供给流寄存器单元。 存储器总线（3）连接在数据存储器和处理器之间，处理器通过该存储器总线访问随机访问的数据。 还包括以下独立权利要求：（1）处理单位; （2）流数据处理系统; 和（3）流注册。

公开(公告)号：EP1378825A1

公开(公告)日：2004-01-07

申请号：EP02425437.7

申请日：2002-07-02

Applicant: STMicroelectronics S.r.l.

Inventor： Rovati, Fabrizio Simone ,  Borneo, Antonio Maria ,  Pau, Danilo Pietro

IPC: G06F9/38

CPC classification number: G06F9/3879 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3885

Abstract: The program to be executed is compiled by translating it into native instructions of the instruction-set architecture (ISA) of the processor system (SILC 1, SILC 2), organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions ("must" instructions), which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions ("can" instructions), which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system (SILC 1, SILC 2), assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set ("must" set) of two successive bundles. The instructions of the sequence may be executed by the various processors of the system (SILC 1, SILC 2) in conditions of binary compatibility.

Abstract translation: 要执行的程序通过将其转换为指令集架构的处理器系统的（ISA）（SILC 1，SILC 2）的本机指令，组织从程序翻译成导出束respectivement的顺序的说明编译 连续束，每个束分组在一起指令angepasst由处理器系统中并行执行。该指令束排序成respectivement子束，所述子束标识第一组指令（“必须”指令），这 必须属于所述顺序的下一个包，以及第二组指令（“罐”指令）的指令，其可以之前和并联相对于属于所述订单的所述随后的包中的指令来执行之前被执行的 ， 有被定义在处理器系统的连续操作周期指令的执行（SILC 1，SILC 2）的序列，在操作循环分配每个子束，从而防止同时分配给两个子束的相同的操作周期 属于第一组的两个连续捆（“必须”设置）。 序列的指令可以由系统中的二进制兼容性的条件的各种处理器（SILC 1，SILC 2）被执行。

公开(公告)号：EP1416393B1

公开(公告)日：2008-08-13

申请号：EP02257603.7

申请日：2002-11-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.l.

Inventor： Homewood, Mark Owen ,  Borneo, Antonio Maria

IPC: G06F13/38

CPC classification number: G06F13/385

公开(公告)号：EP1447742A1

公开(公告)日：2004-08-18

申请号：EP03425081.1

申请日：2003-02-11

Applicant: STMicroelectronics S.r.l.

Inventor： Pagni, Andrea ,  Lucini, Fabrizio ,  Pau, Danillo Pietro ,  Borneo, Antonio Maria ,  Zaccaria, Vittorio

IPC: G06F9/318

CPC classification number: G06F9/30174 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3879

Abstract: A procedure for translating instructions belonging to a first instruction set that can be executed on a processor of the ARM type into instructions belonging to a second instruction set that can be executed on a processor of the LX type comprising a core provides a first set of registers corresponding to the instructions that can be executed on a processor of the ARM type and a second set of registers corresponding to the instructions that can be executed on a processor of the LX type.
Each register of said first set is mapped in a corresponding register of said second set designed to emulate the behaviour of the first register, obtaining a unique independent translation of the data of said first instruction set into said second instruction set. Said translation is performed by means of a translation device external to the core of the processor of the LX type, said core remaining therefore unaltered, in particular with reference to its issue logic, and the translation operating in the absence of access to the resources of said core, by means of interception, by the translation device, of the accesses of the core to the storage area reserved to the ARM instructions.
Preferential application is to an ST-200 LX microprocessor.

Abstract translation: 一种用于转换属于第一指令集的指令的程序也可以在ARM型处理器上执行到属于第二指令集的指令也可以在LX类型包括芯的处理器上被执行时提供第一组寄存器 对应于该指令也可以在ARM类型和第二组寄存器对应于指令中的处理器上执行并可以在LX类型的处理器上被执行。 所述第一组的每个寄存器中对应的所述第二组设计用于模拟所述第一寄存器的行为，获得所述第一指令集到所述第二指令集的数据的一个唯一的独立的翻译的一个寄存器被映射。 所述翻译由翻译装置外部的LX类型的处理器核心来执行，所述芯剩余THEREFORE不变，特别是参照其发布逻辑，和翻译在没有接触的操作以资源 所述核心，通过拦截的装置，它由所述翻译装置中，芯到保留给ARM指令的存储区域的访问的。 优先应用是ST-200 LX微处理器。

公开(公告)号：EP1126729A1

公开(公告)日：2001-08-22

申请号：EP00830113.7

申请日：2000-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Borneo, Antonio Maria ,  Salinari, Lanfranco

IPC: H04N17/00

CPC classification number: H04N17/00

Abstract: A process for estimating the noise level of a sequence of images comprises the operations of:

producing a local estimate (16) of the noise level of the said images,
creating (18) the histogram of the said estimate,
deriving (20) at least one parameter of the said histogram, and
determining (22), by calculation or by means of an empirical relation, at least one noise level parameter on the basis of the said at least one parameter derived from the histogram.

The corresponding device can be incorporated, for example, in an MPEG-2 encoder, where the parameter (NL) identifying the noise level is used for the adjustment of the internal variables of the encoding process.

Abstract translation: 用于估计图像序列的噪声电平的过程包括以下操作：产生所述图像的噪声电平的局部估计（16），创建（18）所述估计的直方图，至少导出（20） 所述直方图的一个参数，以及基于从所述直方图导出的所述至少一个参数，通过计算或借助经验关系确定（22）至少一个噪声电平参数。 相应的装置可以被合并在例如MPEG-2编码器中，其中标识噪声电平的参数（NL）用于调整编码过程的内部变量。

公开(公告)号：EP1100260A1

公开(公告)日：2001-05-16

申请号：EP99830705.2

申请日：1999-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Borneo, Antonio Maria ,  Salinari, Lanfranco

IPC: H04N5/21 ,  H04N7/26

CPC classification number: G06T5/002 ,  G06T5/20 ,  G06T5/50 ,  G06T2207/10016 ,  G06T2207/20182 ,  H04N5/21 ,  H04N19/80

Abstract: A method of filtering noise of digital pictures comprises selecting a first set of pixels (WORKING_WINDOW) constituted by the union of a pixel of the current picture to be filtered (P) and of a second set of pixels temporally and spatially near (PIXEL_NEAR) to said pixel, calculating a certain number (N) of extended sums (SUMk j ) of values assumed by as many pre-established weight functions of the intensity of a selected video component (k j ) on the first set of pixels (WORKING_WINDOW). The pixels of the second set of pixels near (PIXEL_NEAR) can belong to the current picture or to a preceding picture.
Several noise filters for digital pictures implementing the method of the invention are also presented.

Abstract translation: 滤波数字图像的噪声的方法包括：选择由当前图像的被滤波图像（P）的像素和时间和空间上的第二组像素（PIXEL_NEAR）组合而构成的第一组像素（WORKING_WINDOW）到 计算由第一组像素（WORKING_WINDOW）上的所选择的视频分量（kj）的强度的许多预先建立的权重函数假设的值的一定数量（N）的扩展和（SUMkj）。 靠近（PIXEL_NEAR）的第二组像素的像素可以属于当前图像或前一图像。 还介绍了实现本发明方法的数字图像的几个噪声滤波器。