公开(公告)号：EP1445734A1

公开(公告)日：2004-08-11

申请号：EP03002728.8

申请日：2003-02-06

Applicant: STMicroelectronics S.r.l.

Inventor： Gardella, Pierluigi Michele ,  Barone, Massimiliano ,  Alfonso, Daniele ,  Pau, Danilo Pietro ,  Lavigna, Daniele

IPC: G06T9/00

CPC classification number: G06T9/005

Abstract: A method for texture compressing images having a plurality of color components (R, G, B), includes the step of decomposing the images in sub-blocks each including only one color component. At least one first predictor is defined for each said sub-block and a respective set of prediction differences is computed for each sub-block. Then the prediction differences for each sub block are sorted, and a look-up prediction differences palette is set up by defining therefrom a look-up prediction error palette. A code is associated with each column of the error palette.

Abstract translation: 一种用于对具有多个颜色分量（R，G，B）的图像进行纹理压缩的方法包括在每个仅包括一个颜色分量的子块中分解图像的步骤。 为每个所述子块定义至少一个第一预测器，并为每个子块计算相应的一组预测差异。 然后对每个子块的预测差异进行排序，并且通过定义查找预测误差调色板来建立查找预测差异调色板。 代码与错误调色板的每一列相关联。

公开(公告)号：EP1378999A1

公开(公告)日：2004-01-07

申请号：EP02425440.1

申请日：2002-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pau, Danilo Pietro ,  Piccinelli, Emiliano Mario Angelo ,  Sannino, Roberto

IPC: H03M7/30 ,  G06F9/45 ,  H03M7/40

CPC classification number: H03M7/30 ,  H03M7/3082 ,  H03M7/40

Abstract: Binary words are converted between a non-encoded format (OP) and a compressed encoded format (V), in which the binary words are, at least in part, represented by encoded bit sequences that are shorter than the respective binary word in the non-encoded format. The shortest encoded bit sequences are selected according to the statistical recurrence of the respective words in the non-encoded format, and associated to the binary words with higher recurrence are encoded bit sequences comprising bit numbers that are accordingly smaller. The correspondence between binary words in non-encoded format and the encoded bit sequences associated to them is established by means of indices of an encoding vocabulary. The conversion process comprises the operations of:

arranging the indices according to an ordered sequence;
organizing the sequence of indices into groups of vectors (GV);
splitting each group of vectors into a given number of vectors (V); and
encoding the vectors (V) independently from one another.

Alternatively, for each group of vectors, at the end of the encoding process, calculation is carried out - the result being saved in a table, referred to as address-translation table (ATT) - of the starting address on 32 bits of the compressed block or of the differences, expressed in bytes, with respect to the last complete address appearing in said table (ATT).

Abstract translation: 二进制字在非编码格式（OP）和压缩编码格式（V）之间转换，其中二进制字至少部分地由比非非编码格式（OP）中的相应二进制字短的编码比特序列表示 编码格式。 根据非编码格式的各个字的统计重复来选择最短的编码比特序列，并且与具有较高重复次数的二进制字相关联的编码比特序列是包括相应较小的比特数的编码比特序列。 非编码格式的二进制字与与其相关联的编码比特序列之间的对应关系通过编码词汇的索引建立。 转换过程包括以下操作：根据有序序列排列索引; 将指数序列组织成向量组（GV）; 将每组向量分解为给定数量的向量（V）; 并且彼此独立地编码矢量（V）。 或者，对于每个向量组，在编码处理结束时，执行计算 - 结果被保存在32（32）的起始地址的称为地址转换表（ATT）的表中 相对于出现在所述表（ATT）中的最后一个完整地址，压缩块的位或以字节表示的差的位。

公开(公告)号：EP1496704A1

公开(公告)日：2005-01-12

申请号：EP03015269.8

申请日：2003-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Sirtori, Daniele ,  Pau, Danilo Pietro ,  Gardella, Pierluigi ,  Barone, Massimiliano ,  Falchetto, Mirko

IPC: H04N7/26

CPC classification number: G06T15/005 ,  G06T9/001 ,  H04N19/29 ,  H04N19/31 ,  H04N19/42 ,  H04N19/517 ,  H04N19/537 ,  H04N19/577 ,  H04N19/587

Abstract: A graphic system comprising a pipelined tridimensional graphic engine for generating image frames for a display inlcudes a graphic engine (110;210) comprising at least one geometric processing elaboration stages (111, 112), performing motion motion extraction. The engine also includes a rendering stage (113) generating full image frames (KF) at a first frame rate (F2) to be displayed at a second frame rate (F1), higher than the first frame rate (F2). The pipelined graphic engine further comprises a motion encoder (214) receiving motion vector information (MB) and suitable for coding the motion information e.g. with a variable length code, while generating a signal (R4) representative of interpolated frames (IF). The motion encoder (214) exploits the motion information (MB) as generated by the geometric elaboration stages (211, 212). A motion compensation stage (237) is provided fed with the signal representative of interpolated frames (IF) and full image frames for generating said the interpolated frames (IF). A preferred application is in graphic engines intended to operate in association with smart displays through a wireless connection, i.e. in mobile phones.

Abstract translation: 一种图形系统，包括用于生成用于显示器的图像帧的流水线三维图形引擎，包括包括至少一个几何处理制作阶段（111,112）的图形引擎（110; 210），执行运动运动提取。 引擎还包括以比第一帧速率（F2）更高的以第二帧速率（F1）显示的以第一帧速率（F2）产生全图像帧（KF）的渲染级（113）。 流水线图形引擎还包括运动编码器（214），其接收运动矢量信息（MB）并且适于对运动信息进行编码。 同时产生表示内插帧（IF）的信号（R4）。 运动编码器（214）利用由几何制作阶段（211,212）产生的运动信息（MB）。 提供运动补偿级（237），其馈送代表内插帧（IF）的信号和用于产生所述内插帧（IF）的全图像帧。 优选的应用是旨在通过无线连接（即在移动电话中）与智能显示器相关联地操作的图形引擎。

公开(公告)号：EP1496704B1

公开(公告)日：2009-01-21

申请号：EP03015269.8

申请日：2003-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Sirtori, Daniele ,  Pau, Danilo Pietro ,  Gardella, Pierluigi ,  Barone, Massimiliano ,  Falchetto, Mirko

IPC: H04N7/26

CPC classification number: G06T15/005 ,  G06T9/001 ,  H04N19/29 ,  H04N19/31 ,  H04N19/42 ,  H04N19/517 ,  H04N19/537 ,  H04N19/577 ,  H04N19/587

公开(公告)号：EP1496475A1

公开(公告)日：2005-01-12

申请号：EP03015270.6

申请日：2003-07-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Limited

Inventor： Barone, Massimiliano ,  Pau, Danilo Pietro ,  Gardella, Pierluigi ,  Goda, Simon James ,  Hill, Stephen Adrian ,  Sweet, Gary James ,  Robart, Mathieu

IPC: G06T15/00 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06T15/40

Abstract: A geometric processing stage (111b) for a pipelined engine for processing video signals and generating processed video signal in space coordinates (S) adapted for display on a screen. The geometric processing stage (111b) includes:

a model view module (201) for generating projection coordinates of primitives of the video signals in a view space, said primitives including visible and non-visible primitives,
a back face culling module (309) arranged downstream of the model view module (201) for at least partially eliminating the non visible primitives,
a projection transform module (204) for transforming the coordinates of the video signals from view space coordinates into normalized projection coordinates (P), and
a perspective divide module (208) for transforming the coordinates of the video signals from normalized projection (P) coordinates into screen space coordinates (S).

The back face culling module (309) is arranged downstream the projection transform module (204) and operates on normalized projection (P) coordinates of said primitives. The perspective divide module (208) is arranged downstream the back face culling module (309) for transforming the coordinates of the video signals from normalized projection (P) coordinates into screen space coordinates (S). A circuit (10) in the back face culling module can be shared with a standard three dimension back face culling operation when necessary.
A preferred application is in graphic engines using standard graphics language like OpenGL and NokiaGL.

Abstract translation: 用于在适用于在屏幕上显示空间坐标（S）的视频信号并产生已处理的视频信号的流水线处理引擎的几何处理级（111B）。 几何处理级（111B），包括：用于在视觉空间生成的原始视频信号的投影坐标的模型视图模块（201），所述原语包括可见和不可见图元，设置在背面剔除模块（309） 用于从视觉空间变换所述视频信号的坐标模型视图模块（201）用于至少部分地消除所述非可见原始，投影变换模块（204）的下游坐标转换成归一化的投影坐标（P），和一个透视分割 模块（208），用于从归一化的投影（P）变换所述视频信号的坐标坐标转换成屏幕空间坐标（S）。 的背面剔除模块（309）的下游布置在投影变换模块（204）和操作上归一化的投影（P）。所述原始的坐标。 在透视分割模块（208）被布置在下游的背面剔除模块（309），用于从归一化的投影（P）变换所述视频信号的坐标坐标转换成屏幕空间坐标（S）。 所述背面剔除模块中的电路（10）可以与标准三维背面共享剔除操作时是必要的。 一个优选的应用是在使用如OpenGL和NokiaGL标准图形语言的图形引擎。

公开(公告)号：EP1378825A1

公开(公告)日：2004-01-07

申请号：EP02425437.7

申请日：2002-07-02

Applicant: STMicroelectronics S.r.l.

Inventor： Rovati, Fabrizio Simone ,  Borneo, Antonio Maria ,  Pau, Danilo Pietro

IPC: G06F9/38

CPC classification number: G06F9/3879 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3885

Abstract: The program to be executed is compiled by translating it into native instructions of the instruction-set architecture (ISA) of the processor system (SILC 1, SILC 2), organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions ("must" instructions), which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions ("can" instructions), which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system (SILC 1, SILC 2), assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set ("must" set) of two successive bundles. The instructions of the sequence may be executed by the various processors of the system (SILC 1, SILC 2) in conditions of binary compatibility.

Abstract translation: 要执行的程序通过将其转换为指令集架构的处理器系统的（ISA）（SILC 1，SILC 2）的本机指令，组织从程序翻译成导出束respectivement的顺序的说明编译 连续束，每个束分组在一起指令angepasst由处理器系统中并行执行。该指令束排序成respectivement子束，所述子束标识第一组指令（“必须”指令），这 必须属于所述顺序的下一个包，以及第二组指令（“罐”指令）的指令，其可以之前和并联相对于属于所述订单的所述随后的包中的指令来执行之前被执行的 ， 有被定义在处理器系统的连续操作周期指令的执行（SILC 1，SILC 2）的序列，在操作循环分配每个子束，从而防止同时分配给两个子束的相同的操作周期 属于第一组的两个连续捆（“必须”设置）。 序列的指令可以由系统中的二进制兼容性的条件的各种处理器（SILC 1，SILC 2）被执行。

公开(公告)号：EP1445734B1

公开(公告)日：2007-08-08

申请号：EP03002728.8

申请日：2003-02-06

Applicant: STMicroelectronics S.r.l.

Inventor： Gardella, Pierluigi Michele ,  Barone, Massimiliano ,  Alfonso, Daniele ,  Pau, Danilo Pietro ,  Lavigna, Daniele

IPC: G06T9/00

CPC classification number: G06T9/005

公开(公告)号：EP1443461B1

公开(公告)日：2006-11-02

申请号：EP03002205.7

申请日：2003-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Barone, Massimiliano ,  Vitali, Andrea ,  Pau, Danilo Pietro ,  Sirtori, Daniele ,  Lavigna, Daniele ,  Gardella, Pierluigi

IPC: G06T9/00

CPC classification number: G06T9/005

公开(公告)号：EP1378999B1

公开(公告)日：2005-12-14

申请号：EP02425440.1

申请日：2002-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pau, Danilo Pietro ,  Piccinelli, Emiliano Mario Angelo ,  Sannino, Roberto

IPC: H03M7/30 ,  G06F9/45 ,  H03M7/40

CPC classification number: H03M7/30 ,  H03M7/3082 ,  H03M7/40

公开(公告)号：EP1445958A1

公开(公告)日：2004-08-11

申请号：EP03002443.4

申请日：2003-02-05

Applicant: STMicroelectronics S.r.l.

Inventor： Filippini, Gianluca ,  Piccinelli, Emiliano Mario ,  Pau, Danilo Pietro

IPC: H04N7/26 ,  H04N7/50

CPC classification number: H04N19/90 ,  H04N19/124 ,  H04N19/126 ,  H04N19/40

Abstract: Digital signals are converted between a first (IS) and second (OS) format by a conversion process including the step of generating coefficients (X n representing such digital signals. Such coefficients may be e.g. Discrete Cosine Transform (DCT) coefficient generated during encoding/transcoding of MPEG signal. The coefficients are subject to quantization (q) by generating a dither signal (W n ) that is added to the coefficients (X n ) before quantization (q) to generate a quantized signal. Preferably, each coefficient (X n ) is first subject to a first quantization step (q1) in the absence of any dither signal (W n ) added to generate an undithered quantized coefficient. If the undithered quantized signal is equal to zero the undithered quantized coefficient is taken as the output quantized signal. If the undithered quantized coefficient is different from zero, the dither signal (W n ) is added and the dithered coefficient thus obtained is subject to a quantization step (q2) to generate the output quantized signal.

Abstract translation: 通过包括产生系数（Xn表示这种数字信号）的步骤的转换处理，在第一（IS）和第二（OS）格式之间转换数字信号，这样的系数可以是编码/转码期间产生的离散余弦变换（DCT）系数 通过生成与量化前的系数（Xn）相加的抖动信号（Wn）来生成量化信号，对系数进行量化（q），优选地，每个系数（Xn）是第一 在不加任何抖动信号（Wn）的情况下进行第一量化步骤（q1）以生成未抖动的量化系数，如果未调制的量化信号为零，则将未调制量化系数作为输出量化信号，如果 未校准的量化系数不同于零，将抖动信号（Wn）相加，并且由此获得的抖动系数经受量化步长（q2）以产生outpu t量化信号。