公开(公告)号：EP4174915A1

公开(公告)日：2023-05-03

申请号：EP22198683.9

申请日：2022-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： GRASSO, Agata ,  PILUSO, Nicolò ,  SEVERINO, Andrea ,  CAFRA, Brunella

IPC: H01L21/306

Abstract: A Chemical Mechanical Polishing, CMP, process applied to a wafer (20) of Silicon Carbide having a thickness of, or lower than, 200µm, comprising the steps of: arranging the wafer (20) on a supporting head (14) of a CMP processing apparatus (10), the wafer (20) having a front side (20a) and a back side (20b) opposite to one another, the front side (20a) housing at least one electronic component and being coupled to the supporting head (14); deliver a polishing slurry on the wafer (20), wherein the polishing slurry has a pH in the range 2-3; pressing the back side (20b) of the wafer (20) against a polishing pad (16) of the CMP apparatus (10) exerting, by the supporting head (14), a pressure on the polishing pad (16) in the range 5-20 kPa; setting a rotation of the polishing pad (16) in the range 30-180 rpm, and setting a rotation of polishing head (14) in the range 30-180 rpm; setting and maintaining a CMP process temperature equal to, or below, 50°C.

公开(公告)号：EP4036987A1

公开(公告)日：2022-08-03

申请号：EP22153999.2

申请日：2022-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： RENNA, Crocifisso Marco Antonio ,  LANDI, Antonio ,  CAFRA, Brunella

IPC: H01L29/417 ,  H01L29/739 ,  H01L29/45 ,  H01L21/283 ,  H01L29/78

Abstract: A vertical-conduction semiconductor device (20), in particular a vertical IGBT, is provided with a backside metal structure (30), i.e. the collector electrode in case the device is an IGBT. The device comprises a silicon substrate (22) having a front face (22a) and a rear face (22b); a front-side structure (24) arranged on the front face (22a) of the substrate (22), having at least one current-conduction region at the front face (22a); and a back side metal structure (30), arranged on the rear face (22b) of the substrate (22), in electrical contact with the substrate (22) and constituted by a stack of metal layers. The back side metal structure (30) is formed by: a first metal layer (26); a silicide region (27), interposed between the rear face (22b) of the substrate (22) and the first metal layer (26) and in electrical contact with the aforesaid rear face (22b); and a second metal layer (28) arranged on the first metal layer (26). In one embodiment the silicide layer (27) is a nickel silicide and first metal layer (26) is composed of nickel and vanadium with a vanadium concentration of 5-8%.