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    Electronic memory device having high integration density non volatile memory cells and a reduced capacitive coupling
    2.
    发明公开
    Electronic memory device having high integration density non volatile memory cells and a reduced capacitive coupling 有权
    电子存储装置，其包括具有高集成度和降低的电容耦合的非易失性存储器单元

    公开(公告)号：EP1672646A1

    公开(公告)日：2006-06-21

    申请号：EP05027286.3

    申请日：2005-12-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Caimi, Carlo ,  Mastrodomenico, Giovanni

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115

    Abstract: Flash NAND memory electronic device comprising non-volatile cells and having a high integration density and relative programming method. Memory device (1) of the type integrated on a semiconductor substrate (3) and comprising one matrix (6) with rows or Word lines (4) and columns or Bit lines (5) organised in sectors (7) of memory cells (2). The device (1) comprising between said cells (2) of said opposite Word lines (4) belonging to at least one of said sectors (7) of said matrix (6) a lateral coating (15) along the direction of the Bit lines (5) having at least one conductive layer (16) with a contact terminal (9) being selectively biased or floating during each program, read or erase operation, each cell belonging to said sector (7).

    Abstract translation: 闪速NAND存储器的电子设备，其包括非易失性单元和具有高的集成密度和相对编程方法。 存储器设备（1）集成在一个半导体衬底（3），并包括一种基质的类型（6）的行或字线（4）和列线或位线（5）中的存储单元的扇区（7）主办（2 ）。 的装置（1）所述的细胞（2）所述的相对的字线（4）沿着所述位线的方向属于所述扇区（7）。所述的基质（6）的横向涂层中的至少一个（15）之间，其包括 （5）具有与接触端子（9）被选择性偏置或每个节目期间浮动至少一个导电层（16），读取或擦除操作中，每个小区属于所述扇区（7）。

    Electronic memory device having high density non volatile memory cells and a reduced capacitive interference cell-to-cell
    4.
    发明公开
    Electronic memory device having high density non volatile memory cells and a reduced capacitive interference cell-to-cell 有权
    电子存储装置，包括非易失性存储器单元具有高密度和减小电容的细胞 - 细胞干扰

    公开(公告)号：EP1672645A1

    公开(公告)日：2006-06-21

    申请号：EP05027285.5

    申请日：2005-12-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Caimi, Carlo ,  Mastrodomenico, Giovanni ,  Caprara, Paolo

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115

    Abstract: Electronic memory device with non-volatile memory cells, high density and reduced interference cell-to-cell, of the type integrated on a semiconductor substrate (3) and organised in matrix with rows or Word lines (4) and columns or Bit lines (5) of memory cells (2). Each of said cells (2) comprises at least one floating gate transistor having a floating gate region (9) projecting from said substrate (3) and a control gate region (12) capacitively coupled to said floating gate region (9). Between the cells (2) of said opposite Word lines (4) a lateral coating (15) is provided comprising at least one conductive layer (16) floating along the direction of said Bit lines (5).

    Abstract translation: 具有非易失性存储器单元，高密度和减小的干扰细胞至细胞，集成在一个半导体衬底（3）和组织在一个矩阵的行或字线（4）和列线或位线（所述类型的电子存储器设备 存储器单元5）（2）。 每个所述电池（2）包括至少一个浮动具有（9），从电容性耦合到所述浮栅区域，在所述基片（3）和控制栅极区域（12）突出的浮栅区栅极晶体管（9）。 将细胞（2）之间的所述相对的字线（4）的横向的涂层（15）设置的至少一个包括用导电层（16）沿所述位线的方向浮动的（5）。

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