公开(公告)号：EP2302684A2

公开(公告)日：2011-03-30

申请号：EP10011934.6

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Camalieri, Marco ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a high integration density power MOS device comprising a substrate (10) of a doped semiconductor with a first type of conductivity whereon a semiconductor layer (11) with lower conductivity is formed, transistor elementary structures Ti (i=l..n) comprising body regions (12), arranged above in said semiconductor (11) inside which the source regions (13) are confined; the power MOS device comprises in each of the transistor elementary structures Ti (i=1..n) a gate structure (14) of the type with dual thickness comprising a first thin layer (15) of gate oxide onto which, at least partially, a dielectric layer (17) is overlapped having thickness greater than said first thin layer (15) and defining a central portion (17) delimited by lateral portions (18) of conductive material, said gate structure (14) further comprising a nitride upper portion (19) above the thick dielectric layer (17) and said lateral portions (18) of conductor material.

Abstract translation: 本发明涉及一种高集成度功率MOS器件，其包括具有第一导电类型的掺杂半导体的衬底（10），其中形成具有较低导电性的半导体层（11），晶体管元素结构Ti（i = n）包括主体区域（12），其布置在所述半导体（11）的上方，所述源极区域（13）被限制在所述半导体内部; 功率MOS器件在晶体管单元结构Ti（i = 1.n）的每一个中包括具有双重厚度的类型的栅极结构（14），其包括栅极氧化物的第一薄层（15），至少部分 ，电介质层（17）重叠，其厚度大于所述第一薄层（15），并且限定由导电材料的横向部分（18）限定的中心部分（17），所述栅极结构（14）还包括氮化物层 在厚介电层（17）和导体材料的所述横向部分（18）之上的部分（19）。

公开(公告)号：EP2302684A3

公开(公告)日：2012-03-14

申请号：EP10011934.6

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Camalieri, Marco ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a high integration density power MOS device comprising a substrate (10) of a doped semiconductor with a first type of conductivity whereon a semiconductor layer (11) with lower conductivity is formed, transistor elementary structures Ti (i=l..n) comprising body regions (12), arranged above in said semiconductor (11) inside which the source regions (13) are confined; the power MOS device comprises in each of the transistor elementary structures Ti (i=1..n) a gate structure (14) of the type with dual thickness comprising a first thin layer (15) of gate oxide onto which, at least partially, a dielectric layer (17) is overlapped having thickness greater than said first thin layer (15) and defining a central portion (17) delimited by lateral portions (18) of conductive material, said gate structure (14) further comprising a nitride upper portion (19) above the thick dielectric layer (17) and said lateral portions (18) of conductor material.