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    Power MOS device
    1.
    发明公开
    Power MOS device 审中-公开
    MOS-Leistungsanordnung

    公开(公告)号：EP2302684A2

    公开(公告)日：2011-03-30

    申请号：EP10011934.6

    申请日：2005-11-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Arena, Giuseppe ,  Camalieri, Marco ,  Ferla, Giuseppe

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

    CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

    Abstract: The invention relates to a high integration density power MOS device comprising a substrate (10) of a doped semiconductor with a first type of conductivity whereon a semiconductor layer (11) with lower conductivity is formed, transistor elementary structures Ti (i=l..n) comprising body regions (12), arranged above in said semiconductor (11) inside which the source regions (13) are confined; the power MOS device comprises in each of the transistor elementary structures Ti (i=1..n) a gate structure (14) of the type with dual thickness comprising a first thin layer (15) of gate oxide onto which, at least partially, a dielectric layer (17) is overlapped having thickness greater than said first thin layer (15) and defining a central portion (17) delimited by lateral portions (18) of conductive material, said gate structure (14) further comprising a nitride upper portion (19) above the thick dielectric layer (17) and said lateral portions (18) of conductor material.

    Abstract translation: 本发明涉及一种高集成度功率MOS器件，其包括具有第一导电类型的掺杂半导体的衬底（10），其中形成具有较低导电性的半导体层（11），晶体管元素结构Ti（i = n）包括主体区域（12），其布置在所述半导体（11）的上方，所述源极区域（13）被限制在所述半导体内部; 功率MOS器件在晶体管单元结构Ti（i = 1.n）的每一个中包括具有双重厚度的类型的栅极结构（14），其包括栅极氧化物的第一薄层（15），至少部分 ，电介质层（17）重叠，其厚度大于所述第一薄层（15），并且限定由导电材料的横向部分（18）限定的中心部分（17），所述栅极结构（14）还包括氮化物层 在厚介电层（17）和导体材料的所述横向部分（18）之上的部分（19）。

    Vertical MOS device and method of making the same
    2.
    发明公开
    Vertical MOS device and method of making the same 审中-公开
    垂直MOS器件和它们的制备方法

    公开(公告)号：EP1455397A3

    公开(公告)日：2005-08-17

    申请号：EP03029916.8

    申请日：2003-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

    Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).
    The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps: realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and realising an enrichment region (9) in the JFET area below the thicker layer.

    High-speed MOS-technology power device integrated structure, and related manufacturing process
    4.
    发明公开
    High-speed MOS-technology power device integrated structure, and related manufacturing process 失效
    VDMOS-Leistungsbauteil und Verfahren zur Herstellung desselben

    公开(公告)号：EP1408542A2

    公开(公告)日：2004-04-14

    申请号：EP03025806.5

    申请日：1994-07-14

    Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

    Inventor： Ferla, Giuseppe ,  Frisinam Ferruccio

    IPC: H01L21/336 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78

    CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.

    Abstract translation: 高速MOS技术功率器件集成结构包括形成在第一导电类型的轻掺杂半导体层（1）中的多个基本功能单元，所述基本功能单元包括覆盖第二导电类型的沟道区（6） 通过包括多晶硅层（5）的导电绝缘栅极层（8）; 导电绝缘栅极层（8）还包括叠加在所述多晶硅（5）层上并具有比多晶硅层（5）的电阻率低得多的电阻率的高导电层（9），使得由多晶硅 层（5）由所述高导电层（9）引入的电阻分流，并且导电绝缘栅极（8）层的整体电阻率降低。

    Power MOS device
    8.
    发明公开
    Power MOS device 审中-公开
    MOS功率器件

    公开(公告)号：EP2302684A3

    公开(公告)日：2012-03-14

    申请号：EP10011934.6

    申请日：2005-11-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Arena, Giuseppe ,  Camalieri, Marco ,  Ferla, Giuseppe

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

    CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

    Abstract: The invention relates to a high integration density power MOS device comprising a substrate (10) of a doped semiconductor with a first type of conductivity whereon a semiconductor layer (11) with lower conductivity is formed, transistor elementary structures Ti (i=l..n) comprising body regions (12), arranged above in said semiconductor (11) inside which the source regions (13) are confined; the power MOS device comprises in each of the transistor elementary structures Ti (i=1..n) a gate structure (14) of the type with dual thickness comprising a first thin layer (15) of gate oxide onto which, at least partially, a dielectric layer (17) is overlapped having thickness greater than said first thin layer (15) and defining a central portion (17) delimited by lateral portions (18) of conductive material, said gate structure (14) further comprising a nitride upper portion (19) above the thick dielectric layer (17) and said lateral portions (18) of conductor material.

    Method of manufacturing a power MOS device
    9.
    发明公开
    Method of manufacturing a power MOS device 有权
    制造功率MOS器件的方法

    公开(公告)号：EP1659637A2

    公开(公告)日：2006-05-24

    申请号：EP05025287.3

    申请日：2005-11-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

    CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

    Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of:

    providing a doped semiconductor substrate (10) with a first type of conductivity (N);
    forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-);
    forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom);
    depositing, on the dielectric layer (16), a hard mask layer;
    masking the hard mask layer by means of a masking layer;
    etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16);
    removing the masking layer;
    isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19);
    forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom)
    depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

    Abstract translation: 本发明涉及一种实现高集成度功率MOS器件的方法，包括以下步骤：提供具有第一导电类型（N）的掺杂半导体衬底（10）; 在衬底（10）上形成具有较低导电性（N-）的半导体层（11）; 在半导体层（11）上形成厚度介于3000和13000A（埃）之间的介电层（16）; 在电介质层（16）上沉积硬掩模层; 借助掩模层掩蔽硬掩模层; 刻蚀所述硬掩模层和所述下层电介质层（16）以限定多个硬掩模部分（19）以保护所述电介质层（16）; 去除掩模层; 各向同性和横向蚀刻所述介质层，在所述硬掩模部分（19）下方的所述介质层（16）中形成横向腔; 形成厚度在150与1500埃（埃）之间的栅极氧化物（15），在所述空腔中沉积导体材料（24）并在其上方形成凹槽隔离物（20），该凹陷隔离物（20）与栅极结构 14）包括所述厚介电层（16）和所述栅极氧化物（15）。

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