公开(公告)号：EP1130517A1

公开(公告)日：2001-09-05

申请号：EP00830158.2

申请日：2000-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： De Ambroggi, Luca Giuseppe ,  Campanele, Fabrizio ,  Kumar, Promod ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco

IPC: G06F11/20

CPC classification number: G11C29/78

Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).

Abstract translation: 用于存储器的冗余架构，其中存储器单元阵列被划分成以行和列组织的至少一对存储体或半阵列（EVEN_BANK，ODD_BANK），其可单独寻址（ADDR_latch_E，ADDR_latch_O）; 包括由特定数量的冗余列单元（REDUNDANCY）组成的一定数量的分组的架构考虑将分组数（REDUNDANCY）分成两个分组子集（REDUNDANCY_EVEN，REDUNDANCY_ODD），每个分组可独立于另一个可寻址 通过各自的地址电路提供专用于相应的存储体或半数列（EVEN_BANK，ODD_BANK）的单元的冗余列。

公开(公告)号：EP1130517B1

公开(公告)日：2004-05-26

申请号：EP00830158.2

申请日：2000-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： De Ambroggi, Luca Giuseppe ,  Campanele, Fabrizio ,  Kumar, Promod ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco

IPC: G06F11/20

CPC classification number: G11C29/78