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    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
    2.
    发明公开
    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit 审中-公开
    从交错突发存储器和相应的电路的控制协议的地址释放信号（ALE）的内部再生

    公开(公告)号：EP1122733A1

    公开(公告)日：2001-08-08

    申请号：EP00200752.4

    申请日：2000-03-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Campanale, Fabrizio ,  De Ambroggi, Luca Giuseppe ,  Pascucci, Luigi

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: An interleaved memory readable in sequential access synchronous mode and in random access asynchronous mode, in function of external protocol signals ( ALE; CEn, RD ), has a circuit of internal regeneration of an external input address latch enabling signal ( ALE ), filtered by a second external chip enable signal ( CEn ). The circuit comprises a latch ( LATCH ) storing the external signal ( ALE_EXT ) of input address latch enabling and a NOR gate combining the output ( ALE_BUFF ) of the latch with the second external signal of chip enable ( CEn ) and producing a first internal replica signal of address latch enabling ( ALE_FAST ). Delay circuits in cascade to the output of the latch and in cascade of the input pad of the external signal of chip enable ( CEn ) and logic means combining the internally generated replica signal ( ALE_FAST ) and the signal ( ALE_BUFF ) present at the output of the latch with signals retarded by said delay circuits produce set and reset signals of an output flip-flop outputting a second internally generated reconditioned address latch enabling signal ( ALE ). The reconditioned signal has a raising edge conditionally retarded compared to the raising edge of the external command ( ALE_EXT ) and a duration that is conditionally incremented such to compensate for eventual critical asynchronisms between the two protocol external signals ( ALE_EXT, CEn ) in the different modes of operation of the interleaved memory.

    Abstract translation: 一种交错的存储器可读在顺序访问同步模式和在随机存取异步模式下，在外部协议信号的功能（ALE; CEN，RD）具有外部输入地址锁存器的内部再生的电路启动信号（ALE），通过过滤 第二外部芯片使能信号（CEN）。 该电路包括一个锁存器（LATCH）存储输入地址锁存器的外部信号（ALE_EXT）启用和NOR门的锁存器的输出（ALE_BUFF）相结合的芯片使能（CEN）的第二外部信号，并产生第一内部复制品 地址的信号锁存启用（ALE_FAST）。 在级联延迟电路的锁存器的输出和在芯片的外部信号的输入焊盘的级联使能（CEN）和逻辑装置组合所述内部生成的复制信号（ALE_FAST）和信号（ALE_BUFF）存在的输出 与由所述延迟电路延迟的锁存信号产生置位和复位的输出触发器输出婷第二内部产生的修复地址锁存使能信号（ALE）的信号。 该翻新信号具有上升沿有条件延迟相比于外部命令（ALE_EXT）的上升沿和一个持续时间没有条件指针累加寻求以补偿不同的模式这两种协议的外部信号（ALE_EXT，CEN）之间最终临界异步性 的交错存储器的操作。

    Built-in testing methodology in flash memory
    4.
    发明公开
    Built-in testing methodology in flash memory 有权
    Einbautes Testverfahren在einem Flash Speicher

    公开(公告)号：EP1453062A1

    公开(公告)日：2004-09-01

    申请号：EP03425126.4

    申请日：2003-02-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Kumar, Promod ,  Tomaiuolo, Francesko ,  Nicosia, Pierpaolo ,  De Ambroggi, Luca Giuseppe ,  Pipitone, Francesco

    IPC: G11C29/00

    CPC classification number: G11C29/16 ,  G11C16/04 ,  G11C2029/0401 ,  G11C2029/0405

    Abstract: An effective EWS flow is implemented by expanding the functions of the microcontroller normally embedded in a FLASH EPROM memory device and of the integrated test structures.
    The architecture gives the possibility of executing test routines internally without involving any external complex or expensive test equipment to control the test program. The algorithms are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE purposely provided). Such a GLOBAL CACHE may be downloaded with the desired routine to a TUI block and provides a full test flexibility also at the device debug level.
    Managing test routines by an internal algorithm permits to make the device architecture transparent from a tester point of view, by purposely creating a standard interface with a set of defined commands and instructions to be interpreted by the on board micro and internally executed.

    Abstract translation: 通过扩展通常嵌入在FLASH EPROM存储器件和集成测试结构中的微控制器的功能来实现有效的EWS流程。 该架构提供了在内部执行测试例程的可能性，而不涉及任何外部复杂或昂贵的测试设备来控制测试程序。 这些算法由板载微控制器执行（可能是从嵌入式ROM中读取或从有意提供的GLOBAL CACHE读取）。 这样的GLOBAL CACHE可以以期望的例程下载到TUI块，并且还可以在设备调试级别提供完整的测试灵活性。 通过内部算法管理测试例程允许从测试人员的角度使设备架构透明化，故意创建具有一组定义的命令和指令的标准接口，以由板上微内部执行 。

    Redundancy architecture for an interleaved memory
    5.
    发明公开
    Redundancy architecture for an interleaved memory 有权
    Redundanzarchitektur bei einem verschachtelten Speicher

    公开(公告)号：EP1130517A1

    公开(公告)日：2001-09-05

    申请号：EP00830158.2

    申请日：2000-03-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Ambroggi, Luca Giuseppe ,  Campanele, Fabrizio ,  Kumar, Promod ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco

    IPC: G06F11/20

    CPC classification number: G11C29/78

    Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).

    Abstract translation: 用于存储器的冗余架构，其中存储器单元阵列被划分成以行和列组织的至少一对存储体或半阵列（EVEN_BANK，ODD_BANK），其可单独寻址（ADDR_latch_E，ADDR_latch_O）; 包括由特定数量的冗余列单元（REDUNDANCY）组成的一定数量的分组的架构考虑将分组数（REDUNDANCY）分成两个分组子集（REDUNDANCY_EVEN，REDUNDANCY_ODD），每个分组可独立于另一个可寻址 通过各自的地址电路提供专用于相应的存储体或半数列（EVEN_BANK，ODD_BANK）的单元的冗余列。

    Accelerated carry generation.
    8.
    发明公开
    Accelerated carry generation. 审中-公开
    加速携带生成。

    公开(公告)号：EP1122739A2

    公开(公告)日：2001-08-08

    申请号：EP00830312.5

    申请日：2000-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Ambroggi, Luca Giuseppe ,  Kumar, Promod ,  Campanale, Fabrizio ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Condemi, Carmelo

    IPC: G11C7/10 ,  G06F7/50

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: An address binary counter for a subdivision bank of the cell array of an interleaved memory with burst access enabled by an enabling signal (ENABLE), comprises as many stages as the bits that may be stored in the cells of a row of the bank and a carry calculation network.
    The carry calculation network comprises an ordered group of independent carry generators, each of a certain number of stages, and having its own enabling bit, that are input with a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit.
    The enabling bit of the first carry generator of the ordered group is said enabling signal (ENABLE), and the enabling bit of any other carry generator of the ordered group is the logic AND of said enabling signal and of the input bits of the preceding carry generator of the ordered group.

    Abstract translation: 用于具有通过使能信号（ENABLE）启用的突发访问的交织存储器的单元阵列的细分阵列的地址二进制计数器包括与可以存储在该阵列的一行的单元中的比特以及与 携带计算网络。 进位计算网络包括一组有序的独立进位发生器，每一级具有一定数量的级，并且具有其自己的使能位，输入级的数量等于级数， 有条不紊地从最低位开始。 有序组的第一进位发生器的使能位是所述使能信号（ENABLE），并且有序组的任何其他进位发生器的使能位是所述使能信号和先前进位的输入位的逻辑与 有序组的生成器。

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