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    A circuit for controlling a reference node in a sense amplifier
    1.
    发明公开
    A circuit for controlling a reference node in a sense amplifier 有权
    Lesaltstärkereert Referenzknotens in einemLeseverstärker

    公开(公告)号：EP1324347A1

    公开(公告)日：2003-07-02

    申请号：EP01830817.1

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giove, Salvatore ,  De Ambroggi, Luca ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Promod, Kumar ,  Piazza, Giuseppe ,  Pipitone, Francesco

    IPC: G11C16/28 ,  G11C7/06

    CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C16/28

    Abstract: A circuit (165) is proposed for controlling a reference node (Nr) in a sense amplifier (145) switchable between an operative condition and a stand-by condition, the reference node providing a reference voltage in the operative condition. The circuit includes means (Cp) for bringing the reference node to a starting voltage upon entry into the stand-by condition, first means (Rda1,Rda2) for keeping the reference node at a pre-charging voltage in the stand-by condition, second means (Rdb1,Rdb2) for providing a comparison voltage closer to the pre-charging voltage than the starting voltage, pulling means (Mu1) for pulling the reference node towards a power supply voltage, and control means (210) for activating the pulling means upon entry into the stand-by condition and for disabling the pulling means when the voltage at the reference node reaches the comparison voltage.

    Abstract translation: 提出了一种电路（165），用于控制在可操作状态和待机状态之间切换的读出放大器（145）中的参考节点（Nr），该参考节点在操作状态下提供参考电压。 电路包括用于在进入待机状态时使参考节点进入起始电压的装置（Cp），用于在备用状态下将参考节点保持在预充电电压的第一装置（Rda1，Rda2） 用于提供比起始电压更接近预充电电压的比较电压的第二装置（Rdb1，Rdb2），用于将参考节点拉向电源电压的牵引装置（Mu1），以及用于启动牵引 意味着当进入待机状态时，以及当参考节点处的电压达到比较电压时禁止拉动装置。

    Redundancy architecture for an interleaved memory
    3.
    发明公开
    Redundancy architecture for an interleaved memory 有权
    Redundanzarchitektur bei einem verschachtelten Speicher

    公开(公告)号：EP1130517A1

    公开(公告)日：2001-09-05

    申请号：EP00830158.2

    申请日：2000-03-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Ambroggi, Luca Giuseppe ,  Campanele, Fabrizio ,  Kumar, Promod ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco

    IPC: G06F11/20

    CPC classification number: G11C29/78

    Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).

    Abstract translation: 用于存储器的冗余架构，其中存储器单元阵列被划分成以行和列组织的至少一对存储体或半阵列（EVEN_BANK，ODD_BANK），其可单独寻址（ADDR_latch_E，ADDR_latch_O）; 包括由特定数量的冗余列单元（REDUNDANCY）组成的一定数量的分组的架构考虑将分组数（REDUNDANCY）分成两个分组子集（REDUNDANCY_EVEN，REDUNDANCY_ODD），每个分组可独立于另一个可寻址 通过各自的地址电路提供专用于相应的存储体或半数列（EVEN_BANK，ODD_BANK）的单元的冗余列。

    Pre-charging circuit of an output buffer
    4.
    发明公开
    Pre-charging circuit of an output buffer 审中-公开
    Vorladeschaltungfüreinen Ausgangspuffer

    公开(公告)号：EP1122887A1

    公开(公告)日：2001-08-08

    申请号：EP00830368.7

    申请日：2000-05-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicosia, Salvatore

    IPC: H03K19/017 ,  H03K19/003 ,  G11C7/10

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: A pre-charging circuit of the output node of an output buffer (BUFFOUT) of an integrated digital system generating at least a first pulse (DLATCHN) for enabling the external visibility of a new datum (DATA) and a second pulse (LOAD) having a shorter duration than the first pulse (DLATCHN) for loading the new datum (DATA) in an output data register (DATABUS_LATCH) whose output is coupled to the input of said output buffer (BUFFOUT) , includes a capacitor (INTERNAL_CAPACITOR) connectable in parallel to the load capacitance of the output node ( IO_pad ) of the buffer by means of a second pass-gate enabled by a pre-charge command (PRECHARGE) corresponding to the logic AND of said second pulse (LOAD) and of the logic XOR of the new datum (DATA) and of the datum (OUT) currently present on the output node ( IO_pad ), and a driver (D) , disabled by said enabling first pulse (DLATCHN) charging said capacitor (INTERNAL_CAPACITOR) to a voltage (VC) corresponding to the logic level of a datum belonging to the group composed of said new datum (DATA) and the logic inversion of the current datum (OUT).

    Abstract translation: 产生至少第一脉冲（DLATCHN）的集成数字系统的输出缓冲器（BUFFOUT）的输出节点的预充电电路，用于实现新数据（DATA）的外部可见性和具有第二脉冲（LOAD）的第二脉冲（LOAD） 比用于将输出耦合到所述输出缓冲器（BUFFOUT）的输入端的输出数据寄存器（DATABUS_LATCH）中的新数据（DATA））加载的第一脉冲（DLATCHN）更短的持续时间包括可并联连接的电容器（INTERNAL_CAPACITOR） 与通过对应于所述第二脉冲（LOAD）的逻辑AND的预充电命令（PRECHARGE）使能的第二传递门和所述第二脉冲（LOAD）的逻辑“与”的逻辑异或相关的第二传递门到所述缓冲器的输出节点（IO_pad）的负载电容 当前存在于输出节点（IO_pad）上的新数据（DATA）和数据（OUT）以及由所述使能第一脉冲（DLATCHN）禁用的驱动器（D），将所述电容器（INTERNAL_CAPACITOR）充电到电压 ）对应于属性属性的逻辑级别 到由所述新数据（DATA）组成的组和当前数据（OUT）的逻辑反转。

    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
    7.
    发明公开
    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit 审中-公开
    从交错突发存储器和相应的电路的控制协议的地址释放信号（ALE）的内部再生

    公开(公告)号：EP1122733A1

    公开(公告)日：2001-08-08

    申请号：EP00200752.4

    申请日：2000-03-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Campanale, Fabrizio ,  De Ambroggi, Luca Giuseppe ,  Pascucci, Luigi

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: An interleaved memory readable in sequential access synchronous mode and in random access asynchronous mode, in function of external protocol signals ( ALE; CEn, RD ), has a circuit of internal regeneration of an external input address latch enabling signal ( ALE ), filtered by a second external chip enable signal ( CEn ). The circuit comprises a latch ( LATCH ) storing the external signal ( ALE_EXT ) of input address latch enabling and a NOR gate combining the output ( ALE_BUFF ) of the latch with the second external signal of chip enable ( CEn ) and producing a first internal replica signal of address latch enabling ( ALE_FAST ). Delay circuits in cascade to the output of the latch and in cascade of the input pad of the external signal of chip enable ( CEn ) and logic means combining the internally generated replica signal ( ALE_FAST ) and the signal ( ALE_BUFF ) present at the output of the latch with signals retarded by said delay circuits produce set and reset signals of an output flip-flop outputting a second internally generated reconditioned address latch enabling signal ( ALE ). The reconditioned signal has a raising edge conditionally retarded compared to the raising edge of the external command ( ALE_EXT ) and a duration that is conditionally incremented such to compensate for eventual critical asynchronisms between the two protocol external signals ( ALE_EXT, CEn ) in the different modes of operation of the interleaved memory.

    Abstract translation: 一种交错的存储器可读在顺序访问同步模式和在随机存取异步模式下，在外部协议信号的功能（ALE; CEN，RD）具有外部输入地址锁存器的内部再生的电路启动信号（ALE），通过过滤 第二外部芯片使能信号（CEN）。 该电路包括一个锁存器（LATCH）存储输入地址锁存器的外部信号（ALE_EXT）启用和NOR门的锁存器的输出（ALE_BUFF）相结合的芯片使能（CEN）的第二外部信号，并产生第一内部复制品 地址的信号锁存启用（ALE_FAST）。 在级联延迟电路的锁存器的输出和在芯片的外部信号的输入焊盘的级联使能（CEN）和逻辑装置组合所述内部生成的复制信号（ALE_FAST）和信号（ALE_BUFF）存在的输出 与由所述延迟电路延迟的锁存信号产生置位和复位的输出触发器输出婷第二内部产生的修复地址锁存使能信号（ALE）的信号。 该翻新信号具有上升沿有条件延迟相比于外部命令（ALE_EXT）的上升沿和一个持续时间没有条件指针累加寻求以补偿不同的模式这两种协议的外部信号（ALE_EXT，CEN）之间最终临界异步性 的交错存储器的操作。

    Circuit for managing the transfer of data streams from a plurality of sources within a system
    10.
    发明公开
    Circuit for managing the transfer of data streams from a plurality of sources within a system 审中-公开
    Schallung zur Steuerung vonDatenströmenübertragungaus mehrerer Quellen eines Systems

    公开(公告)号：EP1122737A1

    公开(公告)日：2001-08-08

    申请号：EP00830364.6

    申请日：2000-05-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomaiuolo, Francesco ,  Campanale, Fabrizio ,  Nicosia, Salvatore ,  De Ambroggi, Luca Giuseppe ,  Kumar, Promod

    IPC: G11C7/00

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: The transfer of data within a system having a plurality of data sources (ASYNC BLOCK asynchronous and/or having different bitrates, to produce an output data stream (OUT) synchronous with a certain external timing signal (CLOCK, RD) of request of updating of the datum currently present at the output, is managed by a circuit that includes an output register (OUT REG) in which the datum to be made available at the output is stored and at least an output buffer (OUT BUFF) driving an external data line and functionally coupled to the output of said output register (OUT REG). Each data source (ASYN_BLOCK ) has a data loading register (REG ), a selection multiplexer (MUX) of data to be transferred from one or another of said loading registers to said output register (OUT REG). A central control unit (CPU) produces a plurality of control signals (START , REQ , PRIORITY , CLOCK, RD, GLOBAL_RESET). The circuit managing the transfer (SYNC_ASYN CONTROL) includes a plurality of identical circuits, each dedicated to one of said data sources and composed of a coincidence detecting circuit with hooking (COINCIDENCE DETECTOR WITH HOOKING) input with the logic end signal (PULSE) of said external timing signal (CLOCK RD) and of a selection signal (REQ ) of the source of the datum to be produced in output, and a confirmation signal (DATA_READY ) of availability of the datum at the output of said selected source, outputting in a stretching signal (OK_STR), and of a conditioned update path of the output datum constituted by a first bistable circuit (LATCH UPDATE FLAG) set by the inverted confirmation signal (DATA_READY ) and reset by the logic OR of a global reset command (GLOBAL_RESET) generated by the central control unit (CPU) and of the logic OR of the timing signal (CLOCK) and of the stretching signal (OK_STR), outputting a first flag (OK_UPDATE) of enablement of the updating; a second bistable circuit (ENABLING FLAG OF OUT REG UPDATE) set by the output of said detecting circuit and reset by the logic OR of the signal (GLOBAL_RESET) and of a signal (NEW_OUT) corresponding to the logic OR of signals (NEW_OUT ) coming from the respective data sources , outputting an update flag (PRE_LOAD); a logic OR gate, input with the update flag (PRE-LOAD) and with the logic OR signal of the signal (PULSE) and of the stretching signal (OK_STR) and producing in output a selection signal (LOAD ) for the multiplexer (MUX); a pass-gate coupling the input of an output buffer OUT BUFF to the respective output register OUT REG, enabled by the logic OR signal (NEW_OUT) of the signals (NEW_OUT ), each corresponding to the logic OR of the signal (PULSE) and of the stretching signal (OK_STR) of the managing circuit (block ) of a respective data source.

    Abstract translation: 具有异步和/或具有不同比特率的多个数据源（ASYNC BLOCK <1：n>）的系统内的数据传送，以产生与某个外部定时信号（CLOCK，RD）同步的输出数据流（OUT） 更新当前存在于输出端的数据的请求由包括输出寄存器（OUT REG）的电路管理，其中存储在输出端可用的数据，并且至少输出缓冲器（OUT BUFF） 每个数据源（ASYN_BLOCK <1：n>）都有一个数据加载寄存器（RE​​G <1：n>），一个选择多路复用器（MUX） ）从一个或另一个所述加载寄存器传送到所述输出寄存器（OUT REG）的数据，中央控制单元（CPU）产生多个控制信号（START <1：n>，REQ <1：n> ，优先，CLOCK，RD，GLOBAL_RESET）。管理传输的电路（SYNC_ASYN CONTROL）包括多个 每个专用于所述数据源中的一个，并由具有与所述外部定时信号（CLOCK RD）的逻辑结束信号（PULSE））和选择信号（PORSE）一起输入的具有挂钩（具有HOOKING的COINCIDENCE检测器）的符合检测电路组成 （REQ i），以及在所述选择的源的输出处的数据的可用性的确认信号（DATA_READY ），以拉伸信号（OK_STR）输出， 以及由由反相确认信号（DATA_READY i）设置的第一双稳态电路（LATCH UPDATE FLAG）构成的输出数据的调节更新路径，并由由所述反相确认信号（DATA_READY）产生的全局复位命令（GLOBAL_RESET）的逻辑OR复位 中央控制单元（CPU）和定时信号（CLOCK）和拉伸信号（OK_STR）的逻辑或运算，输出启动更新的第一标志（OK_UPDATE）; 由所述检测电路的输出设置的第二双稳态电路（ENABLING FLAG OF OUT REG UPDATE），并由信号（GLOBAL_RESET）的逻辑或与信号（NEW_OUT ），输出更新标志（PRE_LOAD）; 逻辑或门，用更新标志（PRE-LOAD）和信号（PULSE）的逻辑或信号和拉伸信号（OK_STR）输入，并在输出中产生选择信号（LOAD ），用于 多路复用器（MUX）; 将输出缓冲器OUT BUFF的输入耦合到各个输出寄存器OUT REG的通过门，该寄存器通过信号（NEW_OUT i）的逻辑“或”信号（NEW_OUT）使能，每个对应于信号的逻辑或 PULSE）和相应数据源的管理电路（块i）的拉伸信号（OK_STR）。

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