公开(公告)号：EP1804289A3

公开(公告)日：2008-10-22

申请号：EP06026787.9

申请日：2006-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Capetti, Gianfranco ,  Cantú, Pietro

IPC: H01L21/8247 ,  H01L27/115 ,  G03F1/14 ,  H01L21/768

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521

Abstract: A non volatile memory device is described being integrated on semiconductor substrate (11, 110) and comprising a matrix of non volatile memory cells (12, 120) organised in rows, called word lines, and columns, called bit lines, the device comprising:
- a plurality of active areas (13, 130) formed on the semiconductor substrate (11, 110) comprising a first and a second group (G1, G2; G3, G4) of active areas,
- the non volatile memory cells (12, 120) being integrated in the first group (G1, G3) of active areas, each non volatile memory cell (12, 120) comprising a source region, a drain region and a floating gate electrode coupled to a control gate electrode, at least one group (14, 140) of the memory cells (12, 120) sharing a common source region (15, 150) integrated on the semiconductor substrate (11, 110), the device being characterised in that:

- said plurality of active areas (13, 130) are equidistant from each other,
- a contact region (16, 160) is integrated in the second group (G2, G4) of active areas (13, 130) and is provided with at least one common source contact (17, 170) of said common source region (15, 150).

公开(公告)号：EP1804289A2

公开(公告)日：2007-07-04

申请号：EP06026787.9

申请日：2006-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Capetti, Gianfranco ,  Cantú, Pietro

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521

Abstract: A non volatile memory device is described being integrated on semiconductor substrate (11, 110) and comprising a matrix of non volatile memory cells (12, 120) organised in rows, called word lines, and columns, called bit lines, the device comprising:
- a plurality of active areas (13, 130) formed on the semiconductor substrate (11, 110) comprising a first and a second group (G1, G2; G3, G4) of active areas,
- the non volatile memory cells (12, 120) being integrated in the first group (G1, G3) of active areas, each non volatile memory cell (12, 120) comprising a source region, a drain region and a floating gate electrode coupled to a control gate electrode, at least one group (14, 140) of the memory cells (12, 120) sharing a common source region (15, 150) integrated on the semiconductor substrate (11, 110), the device being characterised in that:

- said plurality of active areas (13, 130) are equidistant from each other,
- a contact region (16, 160) is integrated in the second group (G2, G4) of active areas (13, 130) and is provided with at least one common source contact (17, 170) of said common source region (15, 150).

Abstract translation: 描述了非易失性存储器件集成在半导体衬底（11,110）上，并且包括被称为位线的称为字线的行的非易失性存储器单元（12,120）的矩阵，所述器件包括： - 形成在半导体衬底（11,110）上的多个有源区（13,130），包括有源区的第一和第二组（G1，G2; G3，G4）， - 非易失性存储单元（12， 120）集成在有源区的第一组（G1，G3）中，每个非易失性存储单元（12,120）包括耦合到控制栅极的源极区，漏极区和浮栅，至少一个 所述存储单元（12,120）的组（14,140）共享共同的半导体衬底（11,110）上的公共源极区域（15,150），所述器件的特征在于： - 所述多个有源区域 13,130）彼此等距， - 接触区域（16,160）被集成在第二组（G2 ，G4）的有源区域（13,130），并且设置有所述公共源极区域（15,150）的至少一个公共源极触点（17,170）。

公开(公告)号：EP1850369A1

公开(公告)日：2007-10-31

申请号：EP06425283.6

申请日：2006-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Piumi, Daniele ,  Capetti, Gianfranco ,  Alba, Simone ,  Demuro, Carlo ,  De Simone, Danilo

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088

Abstract: A process for manufacturing an organic mask for the microelectronics industry, including the steps of: forming an organic layer (3) on a substrate (2); forming an inorganic mask (6a) on the organic layer (3); and etching selectively the organic layer (3) through the inorganic mask (6a). Furthermore, the step of forming the inorganic mask (6a) envisages: forming at least a first auxiliary layer (5) of a first inorganic material on the organic layer (3); forming a mask layer (6) of a second inorganic material different from the first inorganic material on the first auxiliary layer (5); and shaping the mask layer (6) by means of a dual-exposure lithographic process.

Abstract translation: 一种制造用于微电子工业的有机掩模的方法，包括以下步骤：在衬底（2）上形成有机层（3）; 在有机层（3）上形成无机掩模（6a）; 并通过无机掩模（6a）选择性地蚀刻有机层（3）。 此外，形成无机掩模（6a）的步骤设想：在有机层（3）上至少形成第一无机材料的第一辅助层（5）; 在所述第一辅助层（5）上形成与所述第一无机材料不同的第二无机材料的掩模层（6）; 以及通过双曝光光刻工艺成形掩模层（6）。