公开(公告)号：EP1443418A1

公开(公告)日：2004-08-04

申请号：EP03425055.5

申请日：2003-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Campi, Fabio ,  Toma, Mario ,  Lodi, Andrea ,  Cappelli, Andrea ,  Canegallo, Roberto ,  Guerrieri, Roberto

IPC: G06F15/78 ,  G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3877 ,  G06F9/3897 ,  G06F15/7867

Abstract: The present invention relates to digital embedded architecture (1), including a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor (2), structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel (5, 6) comprising a reconfigurable function unit based on a pipelined array (7) of configurable look-up table based cells controlled by a special purpose control unit (8), thus easing the elaboration of critical kernels algorithms.

Abstract translation: 本发明涉及一种数字嵌入式架构（1），包括微控制器和存储器件，适用于数字信号处理中的可重新配置的计算，包括：处理器（2），其被构造为通过一般的实现非常长的指令字精炼模式 以及包括基于由专用控制单元（8）控制的基于可配置的查找表的单元的流水线阵列（7）的可重新配置功能单元（5,6）的附加数据精细化通道（5,6），从而缓解 阐述关键内核算法。