公开(公告)号：EP1605400A1

公开(公告)日：2005-12-14

申请号：EP04425433.2

申请日：2004-06-11

Applicant: STMicroelectronics S.r.l.

Inventor： Spampinato, Giuseppe ,  Pappalardo, Francesco ,  Fodera, Paolo Antonino ,  Virlinzi, Francesco ,  Capra, Alessandro

IPC: G06T1/60 ,  G06T3/40

CPC classification number: G06T3/4015 ,  G06T1/20

Abstract: A color image pixel data processing pipeline for performing, among corrective and image enhancement steps, at least an interpolation on color data to generate triplets located at distinct pixel locations, including among a plurality of defect correction and image enhancement blocks at least a first color interpolation block, generating RGB information for each pixel of the input image pixel pattern, a second color interpolation block receiving the RGB pattern pixels from said first color interpolation block and rendering enhanced RGB pattern pixels, and a plurality of dedicated line memories and delay circuits associated to and cooperating with said interpolation and correction blocks for permitting real-time processing of pixel data, further includes input image pixel pattern data read/write buffers first and second, of identical capacity suitable to store a subset or pixel block (m*n) of the image data, for translating the scanning mode of pixel data being fed to the input line memory and delay circuits associated to al least said first color interpolation block of said pipeline, from linewise to columnwise, for each subset of data stored in said first and second buffers.
The switching from linewise writing to columnwise reading of the data temporarily stored in input buffer means, reduces overall memory requisite without sensibly increasing computational overhead.

公开(公告)号：EP1416720A1

公开(公告)日：2004-05-06

申请号：EP02425655.4

申请日：2002-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Capra, Alessandro ,  Mancuso, Massimo ,  Broquin, Hervé ,  Fodera, Paolo Antonio ,  Salurso, Elena

IPC: H04N1/64

CPC classification number: H04N1/648

Abstract: Digital video signals, such as the signals generated by an image sensor (1) in a Bayer format, in which the pixels of each line are alternatively coded with two colours, and then converted into an encoded format. In the encoded format, the pixels of the digital video signals are reordered into sets of adjacent pixels, such that the sets group pixels coding the same colour. The encoded signal data is suitable for transmission over a bus (B) in conditions of reduced switching activity.

Abstract translation: 以Bayer格式（1），其中每行的象素被交替地与两种颜色编码时，数字视频信号被转换成将视频信号的像素被记录到组相邻像素的检查的确组的集编码的格式 像素编码有相同的颜色。 编码信号的数据是适合于减小的开关活动期间传输通过总线（B）。 因此独立claimsoft包括用于数字视频信号转换系统。

公开(公告)号：EP1717753A2

公开(公告)日：2006-11-02

申请号：EP06112972.2

申请日：2006-04-24

Applicant: STMicroelectronics S.r.l.

Inventor： Spampinato, Giuseppe ,  Capra, Alessandro ,  Pappalardo, Francesco

IPC: G06T1/60

CPC classification number: G06T1/60

Abstract: An image generating pipeline (IGP) includes a digital signal processor for implementing processing blocks connected in cascade for processing an input image that includes an array of raw pixel values to generate a color image that includes an array of reconstructed pixel values. A memory is coupled to the digital signal processor for storing the raw pixel values and the array of reconstructed pixel values. The digital signal processor includes a data cache, and the raw pixel values of the input image are processed through the processing blocks in sub-arrays having fractional dimensions of the pixel dimensions of the whole image array. The sub-arrays include an input sub-array of pixel values being loaded from the memory for defining a working window. The sub-arrays of raw pixel values have a row-wise dimension of at least a fraction of a full row of the input image, and a column-wise dimension equal to or larger than a column-wise filtering action of a respective processing block to which the input sub-array is input. The digital signal processor outputs at least one fraction of full rows of completely reconstructed pixel values of the input image for storing in the memory.

Abstract translation: 图像生成流水线（IGP）包括数字信号处理器，用于实现级联连接的处理块，用于处理包括原始像素值阵列的输入图像，以生成包括重构像素值阵列的彩色图像。 存储器耦合到数字信号处理器，用于存储原始像素值和重构像素值的阵列。 数字信号处理器包括数据高速缓存，并且通过具有整个图像阵列的像素尺寸的分数维的子阵列中的处理块来处理输入图像的原始像素值。 子阵列包括从存储器加载的用于定义工作窗口的像素值的输入子阵列。 原始像素值的子阵列具有输入图像的完整行的至少一部分的行方向尺寸，以及等于或大于相应处理块的逐列滤波动作的列方向尺寸 输入子数组的输入。 数字信号处理器输出用于存储在存储器中的输入图像的完整重建的像素值的至少一部分的全行。