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    Integrated power amplifier which allows parallel connections
    2.
    发明公开
    Integrated power amplifier which allows parallel connections 失效
    Integrierter平行体Verbindungen erlaubenderLeistungsverstärker

    公开(公告)号：EP0913926A1

    公开(公告)日：1999-05-06

    申请号：EP97830560.5

    申请日：1997-10-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Chiozzi, Giorgio ,  Tavazzani, Claudio

    IPC: H03F1/00 ,  H03F3/72

    CPC classification number: H03F3/72

    Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well the heat dissipation to be distributed over a number of devices, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power dissipated.

    Abstract translation: 集成电力运算放大器可替代地以主模式或从模式操作，使得主放大器可以与一个或多个从属放大器并联连接。 这种布置允许驱动非常低的阻抗负载，以及散热分布在多个器件上，从而提高集成电力系统的最大耗散极限。 此外，通过消除镇流电阻，系统可以提供更多的功率，相同的电源电压和更少的功耗消耗。

    A VDMOS transistor protected against overvoltages between source and gate
    3.
    发明公开
    A VDMOS transistor protected against overvoltages between source and gate 失效
    一种集成电路，包括一个VDMOS晶体管，其对源极和栅极之间的过电压保护

    公开(公告)号：EP0936674A1

    公开(公告)日：1999-08-18

    申请号：EP98830056.2

    申请日：1998-02-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Chiozzi, Giorgio ,  Andreini, Antonio

    IPC: H01L29/00 ,  H01L27/02

    CPC classification number: H01L27/0251 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7811

    Abstract: The n-channel VDMOS transistor described is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region (13) and has its gate electrode connected to the gate electrode (17) of the VDMOS transistor, its source region in common with the source region (9) of the VDMOS transistor, and its drain region (30, 31) connected to the p-type junction-isolation region (14). The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

    Abstract translation: 描述n沟道晶体管VDMOS与结隔离集成电路的n型有源区中形成。 为了防止源极和栅极，从而损坏或破坏栅极电介质之间的过电压，p沟道MOS晶体管以相同的有源区域（13）形成，并且具有VDMOS的连接到栅极电极（17）的栅电极 晶体管，连接到p型结隔离区（14）与所述VDMOS晶体管的源极区域（9）共同其源极区域，漏极区域（30，31）。 p沟道MOS晶体管具有VDMOS晶体管的栅极电介质的击穿电压低于阈值电压，从而没它充当电压限制器。

    Circuit and method for detecting load impedance
    8.
    发明公开
    Circuit and method for detecting load impedance 审中-公开
    Schaltung und Verfahren zur Detektierung einer Lastimpedanz

    公开(公告)号：EP1118865A1

    公开(公告)日：2001-07-25

    申请号：EP00830027.9

    申请日：2000-01-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Chiozzi, Giorgio ,  Storti, Sandro

    IPC: G01R27/26

    CPC classification number: G01R27/02 ,  G01R27/26

    Abstract: A device for detecting load impedance, comprising an analog circuit portion, for detecting the impedance value of a load, and a digital circuit portion (2), which is adapted to provide load impedance type information.

    Abstract translation: 一种用于检测负载阻抗的装置，包括用于检测负载的阻抗值的模拟电路部分和适于提供负载阻抗类型信息的数字电路部分（2）。

    Short-circuit protection circuit, particularly for power transistors
    9.
    发明公开
    Short-circuit protection circuit, particularly for power transistors 失效
    Kurzschluss-Schutzschaltung，insbesonderefürLeistungstransistoren

    公开(公告)号：EP0955724A1

    公开(公告)日：1999-11-10

    申请号：EP98830276.6

    申请日：1998-05-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Chiozzi, Giorgio ,  Marcone, Bruno

    IPC: H03F1/52

    CPC classification number: H03F1/523

    Abstract: A short-circuit protection circuit, particularly for power transistors, whose particularity is the fact that it comprises: first means (11) for mirroring the output current of a power transistor (12) which are parallel-connected to the power transistor, and second mirroring means (13, 14) which are series-connected to the first mirroring means (11) and are adapted to emit a current which is correlated to the current mirrored by the first mirroring means, for comparison with a reference current (Iref); the result of the comparison determining the need to intervene or not on the power transistor (12); and in that it further comprises means (16) for sensing the voltage drop across the power transistor which are parallel-connected to the power transistor and to the first mirroring means (11), in order to adjust minimum and maximum values of the current in output from the power transistor, as a function of the voltage that is present across the transistor.

    Abstract translation: 一种特别用于功率晶体管的短路保护电路，其特征在于它包括：用于镜像并联连接到功率晶体管的功率晶体管（12）的输出电流的第一装置（11），和第二 串联连接到第一镜像装置（11）的镜像装置（13,14），并适于发射与第一镜像装置镜像的电流相关的电流，以便与参考电流（Iref）进行比较。 比较结果确定了在功率晶体管（12）上干涉的需要; 并且其还包括用于感测并联连接到功率晶体管和第一镜像装置（11）的功率晶体管两端的电压降的装置（16），以便调整电流的最小值和最大值 作为晶体管两端存在的电压的函数从功率晶体管输出。

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