公开(公告)号：EP0741416B1

公开(公告)日：2001-09-26

申请号：EP95830176.4

申请日：1995-05-02

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Contiero, Claudio ,  Andreini, Antonio

IPC: H01L29/00 ,  H01L27/092 ,  H01L27/06

CPC classification number: H01L29/0878 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

公开(公告)号：EP0936674B1

公开(公告)日：2006-04-26

申请号：EP98830056.2

申请日：1998-02-10

Applicant: STMicroelectronics S.r.l.

Inventor： Chiozzi, Giorgio ,  Andreini, Antonio

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0251 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7811

公开(公告)号：EP0556744B1

公开(公告)日：1999-01-20

申请号：EP93102240.4

申请日：1993-02-12

Applicant: STMicroelectronics S.r.l.

Inventor： Andreini, Antonio ,  Consiglio, Pietro ,  Erratico, Pietro ,  Ravanelli, Enrico Maria Alfonso

IPC: H04M1/74 ,  H04M1/08

CPC classification number: H04M1/74 ,  H04M1/312 ,  H04M1/82

公开(公告)号：EP1487015A1

公开(公告)日：2004-12-15

申请号：EP03425368.2

申请日：2003-06-10

Applicant: STMicroelectronics S.r.l.

Inventor： Andreini, Antonio ,  Cerati, Lorenzo ,  Galbiata, Paola ,  Merlini, Alessandra

IPC: H01L23/485 ,  H01L23/50

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor electronic device is described comprising a die (2) of semiconductor material having a plurality of contact pads (3,8) electrically connected to a support for example through interposition of contact wires, said plurality of contact pads (3,8) comprising signal pads (8) and power pads (3), the device being characterised in that said signal pads (8) are implemented on the die (2) of semiconductor material with a mutual pitch (P2) lower than the pitch (P1) between said power pads (3), and in that the upper metallic layer of the signal pads is thinner than that of the power pads.

Abstract translation: 描述了一种半导体电子器件，其包括具有多个接触焊盘（3,8）的半导体材料的芯片（2），所述接触焊盘（3,8）例如通过插入接触导线而电连接到支撑件，所述多个接触焊盘（3,8）包括 信号焊盘（8）和电源焊盘（3），其特征在于，所述信号焊盘（8）实现在半导体材料的管芯（2）上，其间距（P2）低于第 所述电源焊盘（3），并且信号焊盘的上金属层比电源焊盘更薄。

公开(公告)号：EP0936674A1

公开(公告)日：1999-08-18

申请号：EP98830056.2

申请日：1998-02-10

Applicant: STMicroelectronics S.r.l.

Inventor： Chiozzi, Giorgio ,  Andreini, Antonio

IPC: H01L29/00 ,  H01L27/02

CPC classification number: H01L27/0251 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7811

Abstract: The n-channel VDMOS transistor described is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region (13) and has its gate electrode connected to the gate electrode (17) of the VDMOS transistor, its source region in common with the source region (9) of the VDMOS transistor, and its drain region (30, 31) connected to the p-type junction-isolation region (14). The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Abstract translation: 描述n沟道晶体管VDMOS与结隔离集成电路的n型有源区中形成。 为了防止源极和栅极，从而损坏或破坏栅极电介质之间的过电压，p沟道MOS晶体管以相同的有源区域（13）形成，并且具有VDMOS的连接到栅极电极（17）的栅电极 晶体管，连接到p型结隔离区（14）与所述VDMOS晶体管的源极区域（9）共同其源极区域，漏极区域（30，31）。 p沟道MOS晶体管具有VDMOS晶体管的栅极电介质的击穿电压低于阈值电压，从而没它充当电压限制器。