公开(公告)号：EP1762943A8

公开(公告)日：2007-10-10

申请号：EP05019644.3

申请日：2005-09-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ciccarelli, Luca ,  Magagni, Luca ,  Fazzi, Alberto ,  Canegallo, Roberto ,  Guerrieri, Roberto

IPC: G06F13/40

CPC classification number: H01L25/0657 ,  G06F13/4077 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The invention relates to a chip-to-chip communication system (10) of the type comprising at least a transmitter TX (11) and a receiver RX (12), inserted between a first and a second voltage references (Vdd, GND) and connected to respective transmitter and receiver clock terminal wherein respective transmitter and receiver clock signals (CP, G) are applied, the transmitter TX (11) having an input terminal (TXin) receiving an input data (D) and an output terminal (TXout) connected to an input terminal (RXin) of the receiver RX (12) at a connection block (15), the receiver RX (12) having an output terminal (RXout) issuing an output signal (Q).
Advantageously according to the invention:
- the transmitter TX (11) comprises at least a precharge and an evaluation blocks (18, 19) connected to each other and to the transmitter clock terminal (CP);
- the receiver RX (12) comprises at least a precharge block (25) connected to the receiver clock terminal (G)

the precharge blocks (18, 25) precharging the output terminal (TXout) of the transmitter TX (11) and the input terminal (RXin) of the receiver RX (12), respectively, to a value corresponding to a first voltage reference (Vcc) during a low phase of the transmitter clock signal (CP).

公开(公告)号：EP2075710A2

公开(公告)日：2009-07-01

申请号：EP08022447.0

申请日：2008-12-24

Applicant: STMicroelectronics S.r.l.

Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

IPC: G06F13/42

CPC classification number: H04L7/10 ,  H04L7/0037

Abstract: The invention relates to a communication system between a first and a second independently clocked devices (L,R), in particular chips, comprising, for each device, at least a transmitter (TXL,TXR) and a receiver (RXL,RXR) connected to each other in a crossed way in correspondence of an inter-chip communication channel (ICC). Advantageously according to the invention, the communication system further comprises a synchronizer (40) in turn including at least a first and a second synchronization block (20L,20R), having respective input terminals (INrL,INrR) connected to the receivers (RXL,RXR) and respective output terminals (OUTtL,OUTtR) connected to the transmitters (TXL,TXR) and comprising at least:
- a test pattern generator (23);
- comparison means (21,22) to check a matching between stored and received test pattern signals; and
- a delay block (26) able to change the clock phases.

Abstract translation: 本发明涉及到一个第一和一个第二unabhängig时钟控制装置（L，R）之间的通信系统，特别是芯片，其包括，对于每一个设备，至少一个发送器（TXL，TXR）和接收器（RXL，RXR）连接 海誓山盟在一个芯片间通信信道（ICC）的对应关系的交叉方法。 有利的是雅丁到本发明，该通信系统还包括又一个同步器（40）包括至少一个第一和一个第二同步块（20L，20R），其具有连接到所述接收器respectivement输入端子（INrL，INRR）（RXL， RXR）和相应的输出端子连接到所述发射机（TXL，TXR）和包含至少（OUTtL，OUTtR）： - 测试图案生成器（23）; - 比较装置（21,22），以检查存储和接收的测试模式信号之间的匹配; 和 - 一个延迟块（26），其能够改变时钟相位。

公开(公告)号：EP1940028A1

公开(公告)日：2008-07-02

申请号：EP06027047.7

申请日：2006-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Fazzi, Alberto ,  Guerrieri, Roberto ,  Magagni, Luca ,  Ciccarelli, Luca ,  Canegallo, Roberto

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356165

Abstract: The present invention relates to a asynchronous interconnection system (10) comprising a transmitter circuit (11) and a receiver circuit (12) inserted between inserted between respective first and second voltage references (Vcctx, GNDtx - Vccrx, GNDrx) and having respective transmitter and receiver nodes (TX, RX) coupled in a capacitive manner.
Advantageously according to the invention, the receiver circuit (12) comprises:
- a recovery stage (13) inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) and connected to the receiver node (RX); and
- a state control stage (14), in turn inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) connected to the recovery stage (13) correspondence with a first feedback node (X) providing a first control signal (Recovery Enable) and having a second feedback node (Z*) connected in a feedback manner to the recovery stage (13).
The recovery stage (13) comprises a first feedback loop (Loop 1) connected to the first feedback node (X) and acting in such a way to recover a received voltage signal and a feedback loop (Loop2) connected to the second feedback node (Z*) of the state control stage (14) and acting in such a way to deactivate the recovery feedback on the receiver node (RX) and guarantee that the receiver node (RX) is let in a high impedance state.

Abstract translation: 本发明涉及一种异步互连系统（10），包括发射机电路（11）和插入在相应的第一和第二电压基准（Vcctx，GNDtx-Vccrx，GNDrx）之间的接收机电路（12），并且具有各自的发射机和 接收器节点（TX，RX）以电容方式耦合。 有利地，根据本发明，接收器电路（12）包括： - 插入在接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间并连接到接收器节点（RX）的恢复级（13） ; 以及 - 状态控制级（14），其又插入在与恢复级（13）连接的接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间，与第一反馈节点（X）对应，提供 第一控制信号（恢复使能）并且具有以反馈方式连接到恢复级（13）的第二反馈节点（Z *）。 恢复阶段（13）包括连接到第一反馈节点（X）的第一反馈回路（回路1），并以这样一种方式起作用以恢复接收的电压信号和连接到第二反馈节点的反馈回路（Loop2） 状态控制级（14）的Z *），并以这样一种方式使接收器节点（RX）上的恢复反馈失效，并保证接收器节点（RX）处于高阻抗状态。

公开(公告)号：EP2075708A2

公开(公告)日：2009-07-01

申请号：EP08022446.2

申请日：2008-12-24

Applicant: STMicroelectronics S.r.l.

Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

IPC: G06F13/40

CPC classification number: G06F13/4077 ,  H04L25/0266 ,  H04L25/028

Abstract: The invention relates to a communication system for the connection between timing non correlated synchronous devices of the type comprising at least one transmitter (30) and one receiver (40) inserted between a first and a second voltage reference (Vcc, GND) and connected to each other by means of a transmitting channel (25) in correspondence with respective transmitting (TX) and receiving (RX) terminals. Advantageously according to the invention, the receiver (40) comprises at least one synchronous input stage (41) suitable for receiving on said receiving terminal (RX) a datum (D) and associated with a synchronous output stage (42) suitable for transmitting said datum (D) in a synchronised way with a clock signal (CP) on a synchronised receiving terminal (RXs).
The invention also relates to a method for transmitting a datum (D) from a transmitter (30) to a receiver (40) interconnected by means of a capacitive channel (25) in a communication system for the connection between independently clocked devices.

Abstract translation: 本发明涉及一种用于在包括至少一个发射器（30）和插入在第一和第二电压参考（Vcc，GND）之间的一个接收器（40）的类型的定时非相关同步装置之间的连接的通信系统，并且连接到 彼此通过与相应的发送（TX）和接收（RX）终端相对应的电容或电阻信道（25）来实现。 有利地，根据本发明，接收器（40）包括适于在所述接收终端（RX）上接收数据（D）的至少一个同步输入级（41）并与适于发送所述接收器（40）的同步输出级（42）相关联的至少一个同步输入级 数据（D）以与同步接收终端（RX）上的时钟信号（CP）同步的方式。

公开(公告)号：EP1940028B1

公开(公告)日：2012-02-29

申请号：EP06027047.7

申请日：2006-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Fazzi, Alberto ,  Guerrieri, Roberto ,  Magagni, Luca ,  Ciccarelli, Luca ,  Canegallo, Roberto

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356165

公开(公告)号：EP1865602A1

公开(公告)日：2007-12-12

申请号：EP06011668.8

申请日：2006-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Ciccarelli, Luca ,  Lodi, Andrea

IPC: H03K17/693

CPC classification number: H03K17/693 ,  H03K19/17736 ,  H03K19/17784

Abstract: The invention relates to a T-switch (35) for connecting first, second and third lines (L0, L1, L2) and comprising:
- an input section (31) in turn including fist, second and third input pass transistors (N0, N 1, N2), each connecting a respective line (L0, L1, L2) with a first internal node (int0) of the T-switch (35); (L0, L1, L2)
- an output section (32) in turn including fist, second and third output pass transistors (NO0, NO1, NO2), each connecting a respective line (L0, L1, L2) with a second internal node (intO0) of the T-switch (35); and
- a single buffer stage (33) connected to a first and a second voltage reference (VDD, GNU) and inserted between the first (into) and second internal node (intOO).

Abstract translation: 本发明涉及一种用于连接第一，第二和第三线路（L0，L1，L2）的T开关（35），包括：输入部分（31），其又包括第一，第二和第三输入传输晶体管（N0， N 1，N 2），每个将相应线路（L0，L1，L2）与所述T开关（35）的第一内部节点（int0）连接; （L0，L1，L2） - 输出部分（32）又包括第一，第二和第三输出传输晶体管（NO0，NO1，NO2），每个连接各个线路（L0，L1，L2）与第二内部节点 （int00）; 以及 - 连接到第一和第二参考电压（VDD，GNU）并插入在第一内部节点（第一内部节点）和第二内部节点（intOO）之间）的单个缓冲器级（33）。

公开(公告)号：EP1762943A1

公开(公告)日：2007-03-14

申请号：EP05019644.3

申请日：2005-09-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ciccarelli, Luca ,  Magagni, Luca ,  Fazzi, Alberto ,  Canagallo, Roberto ,  Guerrieri, Roberto

IPC: G06F13/40

CPC classification number: H01L25/0657 ,  G06F13/4077 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The invention relates to a chip-to-chip communication system (10) of the type comprising at least a transmitter TX (11) and a receiver RX (12), inserted between a first and a second voltage references (Vdd, GND) and connected to respective transmitter and receiver clock terminal wherein respective transmitter and receiver clock signals (CP, G) are applied, the transmitter TX (11) having an input terminal (TXin) receiving an input data (D) and an output terminal (TXout) connected to an input terminal (RXin) of the receiver RX (12) at a connection block (15), the receiver RX (12) having an output terminal (RXout) issuing an output signal (Q).
Advantageously according to the invention:
- the transmitter TX (11) comprises at least a precharge and an evaluation blocks (18, 19) connected to each other and to the transmitter clock terminal (CP);
- the receiver RX (12) comprises at least a precharge block (25) connected to the receiver clock terminal (G)

the precharge blocks (18, 25) precharging the output terminal (TXout) of the transmitter TX (11) and the input terminal (RXin) of the receiver RX (12), respectively, to a value corresponding to a first voltage reference (Vcc) during a low phase of the transmitter clock signal (CP).

Abstract translation: 本发明涉及一种包括至少一个发射机TX（11）和接收机RX（12）的芯片到芯片通信系统（10），该接收机RX（12）插入在第一和第二参考电压（Vdd，GND）和 连接到相应的发射机和接收机时钟终端，其中施加相应的发射机和接收机时钟信号（CP，G），发射机TX（11）具有接收输入数据（D）的输入端（TXin）和输出端（TXout） 在连接块（15）处连接到接收器RX（12）的输入端子（RXin），接收器RX（12）具有发出输出信号（Q）的输出端子（RXout）。 有利地，根据本发明： - 发射机TX（11）至少包括预连接和彼此连接的发射机时钟终端（CP）的评估块（18,19）。 - 接收机RX（12）至少包括连接到接收机时钟终端（G）的预充电块（25），预充电块（18,25）对发射机TX（11）的输出端（TXout）和输入 接收器RX（12）的端子（RXin）分别为在发射机时钟信号（CP）的低相位期间对应于第一电压基准（Vcc）的值。