中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

3 records (took 0.02 seconds)

    A method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors
    2.
    发明公开
    A method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors 失效
    制造工艺与精密电阻高击穿电压的MOS晶体管的集成电路

    公开(公告)号：EP0880165A1

    公开(公告)日：1998-11-25

    申请号：EP97830230.5

    申请日：1997-05-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Stucchi, Elena ,  Daffra, Stefano ,  Cereda, Manlio Sergio

    IPC: H01L21/00 ,  H01L21/329 ,  H01L21/8234

    CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L27/0629 ,  H01L29/66166 ,  H01L29/8605

    Abstract: The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips (14) for constituting the gate electrodes of the MOS transistors and portions (16) defining openings (17) for the formation of resistors, low-dose ionic implantation (18) through the implantation mask to form pairs of regions (19, 20) at the sides of the gate strips (14) and resistive regions (21) through the openings, the formation of an insulating layer (30) on the entire structure thus produced, and anisotropic etching of the insulating layer (30) so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask but leaving a residue (22) of insulating material along the edges of the gate strips (14). To compensate for the removal of a surface layer from the resistive regions due to the anisotropic etching, a second low-dose implantation is carried out without masking of the substrate, with a dose and an energy such as to produce a predetermined resistivity for the resistive regions (21) without altering the resistivities of the source and drain regions of the MOS transistors.

    Abstract translation: 描述的方法提供用于多晶硅包括条带的注入掩模（14）的形成构成MOS晶体管的栅电极的部分和（16） - 定义的开口（17），用于电阻器，低剂量的离子注入的形成（ 18）通过上述注入掩模，以形成区域的对（19，20）在栅极条带（14）和电阻性区域（21）通过开口，在整个结构上的绝缘层（30）的形成。因此侧面 产生，并且在绝缘层（30）的各向异性蚀刻，以露出未包括的多晶硅掩模但留下沿着栅极条带（14）的边缘的绝缘材料的残基（22）的基板的面积。 为了补偿用于去除来自电阻区域的表面层的由于各向异性蚀刻，第二低剂量注入被执行，而不在基板的掩蔽，具有剂量和能量：如以产生预定电阻率的电阻 区域（21），而不改变MOS晶体管的源和漏区的电阻率。

Patent Agency Ranking