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    Process for manufacturing an integrated circuit comprising an array of memory cells
    2.
    发明公开
    Process for manufacturing an integrated circuit comprising an array of memory cells 失效
    Herstellungsverfahrenfüreinen integrierten Schaltkreis mit einer Speicherzellenmatrix

    公开(公告)号：EP0892430A1

    公开(公告)日：1999-01-20

    申请号：EP97830359.2

    申请日：1997-07-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Ginami, Giancarlo

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L23/528

    CPC classification number: H01L27/11526 ,  H01L23/5283 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11543 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD), said defining the second strips (17) providing for selectively etching the first and second layers of conductive material (9,11) outside the memory cell array area by means of a first mask (MASK1), and said defining the first strips (22) providing for selectively etching the second layer of conductive material (11), the layer of insulating material (10) and the first layer of conductive material (9) inside the memory cell array area by means of a second mask (MASK2). The first and second masks (MASK1,MASK2) overlap in a boundary region around the memory cell array area, so that the first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

    Abstract translation: 一种用于制造集成电路的方法，包括存储单元阵列，提供：a）在半导体层（6）的存储单元阵列区域中形成用于存储单元的有效区域; b）在所述存储单元的所述有源区上形成栅极氧化物层（8）; c）在整个集成电路上形成第一层导电材料（9）; d）在第一层导电材料（9）上形成一层绝缘材料（10）; e）从存储单元阵列区域的外部去除绝缘材料层（10）; f）在整个集成电路上形成第二层导电材料（11），其在存储单元阵列区域中通过绝缘材料层（10）与第一导电材料层（9）分离，而在存储单元外部 阵列区域直接叠加在所述第一导电材料层（9）上; g）在存储单元阵列区域内部，限定用于形成存储单元阵列（1）的行（3）的第二导电材料层（11）的第一条带（22），以及限定第二条带 用于形成用于将存储单元阵列的行（3）与电路（5，RD）电气互连的互连线（100）的第二层导电材料（11）的第一层（17），所述第二层导电材料（11） 提供通过第一掩模（MASK1）选择性地蚀刻存储器单元阵列区域外的第一和第二导电材料层（9,11），并且所述第一条带（22）提供用于选择性地蚀刻第二层 导电材料（11），绝缘材料层（10）和第一层导电材料（9）通过第二掩模（MASK2）在存储单元阵列区域内。 第一和第二掩模（MASK1，MASK2）在存储单元阵列区域周围的边界区域中重叠，使得第二导电材料层（11）的第一条带（22）和第二条带（17）自动连接 在其各个端部处于所述边界区域。

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