公开(公告)号：WO2011079882A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005931

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICCIARDO, Antonio ,  GHISU, Davide Ugo

Inventor： ROSSI, Sandro ,  RICCIARDO, Antonio ,  GHISU, Davide Ugo

IPC: H03K17/0416 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  B06B1/02

CPC classification number: H03K17/063 ,  B06B1/0215 ,  H03K17/04163 ,  H03K17/162 ,  H03K17/6872

Abstract: A switching circuit (30) is described being inserted between a connection terminal (Xdcr) and an output terminal (LVout) of a transmission channel (1) and of the type comprising at least one first and one second switching transistor (MSW1, MSW2) which are high voltage MOS transistors of complementary type inserted, in series to each other and by having respective equivalent or body diodes (DSW1, DSW2) in anti-series, between the connection terminal (Xdcr) and the output terminal (LVout). Advantageously according to the invention, the switching circuit comprises at least one bootstrap circuit (31) connected to respective first and second control terminals (XG1, XG2) of these at least one first and one second switching transistor (MSW1, MSW2), as well as to respective first and second voltage references (VDD_P, VDD_M) and having values of parasite capacities between these first and second control terminals (XG1, XG2) and at least one first and one second bootstrap node (XB1, XB2) of at least one order of magnitude lower with respect to the gate-source capacities (Csw1, Csw2) of these at least one first and one second switching transistor (MSW1, MSW2).

Abstract translation: 描述了切换电路（30）被插入在传输通道（1）的连接端子（Xdcr）和输出端子（LVout）之间，并且包括至少一个第一和第二开关晶体管（MSW1，MSW2）的类型， （Xdcr）和输出端子（LVout）之间具有反相串联的相应的等效或体二极管（DSW1，DSW2）。 有利地，根据本发明，切换电路包括连接到这些至少一个第一和第二开关晶体管（MSW1，MSW2）的相应的第一和第二控制端子（XG1，XG2）的至少一个自举电路（31），以及 对于相应的第一和第二参考电压（VDD_P，VDD_M），并且具有这些第一和第二控制端子（XG1，XG2）之间的寄生电容值和至少一个第一和第二引导节点（XB1，XB2） 相对于这些至少一个第一和第二开关晶体管（MSW1，MSW2）的栅极 - 源极电容（Csw1，Csw2）的数量级下降。

公开(公告)号：WO2012077145A8

公开(公告)日：2012-06-14

申请号：PCT/IT2010/000493

申请日：2010-12-09

Applicant: STMICROELECTRONICS S.R.L. ,  GHISU, Davide Ugo ,  RICCIARDO, Antonio ,  ROSSI, Sandro

Inventor： GHISU, Davide Ugo ,  RICCIARDO, Antonio ,  ROSSI, Sandro

IPC: B06B1/02 ,  H03K17/10 ,  H03K17/687 ,  H03K17/693

Abstract: A switching circuit (10) for an ultrasound transmission channel (1) is inserted between a connection terminal (Xdcr) and a low voltage output terminal (LVout) and comprising a receiving switch (30) a high voltage clamp circuit (HV1) inserted between the connection terminal (Xdcr) and a central node (Vc), a low voltage clamping switch (25) inserted between said central node (Vc) and a reference voltage (GND), the receiving switch (30) being low voltage and being inserted between the central node (Vc) and the low voltage output terminal (LVout), the clamping switch (25) and the receiving switch (30) being controlled in a complementary way with respect to each other. A transmission channel ( 1) for ultrasound applications is also described comprising at least such a switching circuit (10) and a process for driving said switching circuit (10).

公开(公告)号：WO2011079881A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005930

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  GHISU, Davide Ugo ,  RICCIARDO, Antonio

Inventor： ROSSI, Sandro ,  GHISU, Davide Ugo ,  RICCIARDO, Antonio

IPC: H03K17/06 ,  H03K17/687 ,  H03K17/74 ,  B06B1/02

CPC classification number: H03K17/6872 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/74

Abstract: A clamping circuit (10) to a voltage reference (GND) is described, of the type comprising at least one clamping core (11) connected to an output terminal (HVout) and having a central node (XC) connected to the voltage reference (GND) and in turn including at least one first and one second clamp transistor (MC1; MC2), connected to the central node (XC) and having respective control terminals (XG1, XG2), the clamping core (11) being also connected at the input to a low voltage input driver block (13). Advantageously according to the invention, the clamping core (11) further comprises at least one first switching off transistor (MS1) connected to the output terminal (HVout) and to the first clamp transistor (MC1), as well as a second switching off transistor (MS2) connected to the output terminal (HVout) and to the second clamp transistor (MC2), these first and second clamp transistors (MC1, MC2) being high voltage MOS transistors of complementary type and these first and second switching off transistors (MS1, MS2) being high voltage MOS transistors of complementary type and connected to the first and second clamp transistors (MC1, MC2) by having the respective equivalent or body diodes in anti-series so as to close themselves when the clamping circuit (10) is active and to sustain positive and negative high voltages when the clamping circuit (10) is not active.

Abstract translation: 描述了到电压基准（GND）的钳位电路（10），其类型包括连接到输出端子（HVout）的至少一个夹紧芯部（11），并且具有连接到电压基准的中心节点（XC） GND），并且还包括连接到中心节点（XC）并且具有各自的控制端子（XG1，XG2）的至少一个第一和第二钳位晶体管（MC1; MC2），夹紧芯部（11）也连接在 输入到低电压输入驱动器块（13）。 有利地，根据本发明，夹紧芯（11）还包括连接到输出端（HVout）和第一钳位晶体管（MC1）的至少一个第一截止晶体管（MS1）以及第二截止晶体管 （MC2）连接到输出端子（HVout）和第二钳位晶体管（MC2）的这些第一和第二钳位晶体管（MC1，MC2）是互补型高压MOS晶体管，这些第一和第二截止晶体管 ，MS2）是互补型的高电压MOS晶体管，通过使相应的等效或体二极管反串联以便在钳位电路（10）为 当钳位电路（10）未被激活时，它有效并维持正和负的高电压。

公开(公告)号：EP3025792B1

公开(公告)日：2019-09-04

申请号：EP15196387.3

申请日：2015-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： ROSSI, Sandro ,  GHISU, Davide Ugo ,  QUAGLIA, Fabio ,  LEONE, Antonio Davide

IPC: B06B1/02 ,  G05F3/02 ,  H03K4/94

公开(公告)号：EP3389187A1

公开(公告)日：2018-10-17

申请号：EP18165941.8

申请日：2018-04-05

Applicant: STMicroelectronics S.r.l.

Inventor： TERENZI, Marco ,  GHISU, Davide Ugo

IPC: H03K19/003

CPC classification number: H03K17/0822 ,  B06B1/0253 ,  B06B2201/76 ,  H03K19/00315

Abstract: A high voltage driving circuit (20, 40) for driving a load (23), configured to receive a low voltage input signal (LVIN; DINP, DINM) and to generate a high voltage output signal (HVOUT), comprising a short circuit protection circuit (30).
Such a short circuit protection circuit (30) comprises a first electronic switch (32) operated by the low voltage input signal (LVIN; DINP, DINM), and a second electronic switch (36) operated by a low voltage signal (LVOUT) obtained by applying a voltage division (24; 47) to the output high voltage signal (HVOUT),
said first electronic switch (32) causing a first pull-up current (M*I 1 ) to be sent to a capacitive element (CL) whose voltage controls the input of a threshold comparator (37),
said second electronic switch (36) causing a second pull-down current (k*N*I 2 ) to be drawn from said capacitive element (CL) whose voltage controls the input of said threshold comparator (37),
a short circuit detection signal (SCF) being picked up at the output of said threshold comparator (37), indicating said short circuit and capable of inhibiting the operation of said electronic driving circuit (20, 40).

公开(公告)号：EP3174203B1

公开(公告)日：2019-12-25

申请号：EP16176683.7

申请日：2016-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： BIANCHI, Dario ,  GUANZIROLI, Federico ,  GHISU, Davide Ugo

IPC: H03K3/356 ,  H03K19/0185

公开(公告)号：EP3174203A1

公开(公告)日：2017-05-31

申请号：EP16176683.7

申请日：2016-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： BIANCHI, Dario ,  GUANZIROLI, Federico ,  GHISU, Davide Ugo

IPC: H03K3/356 ,  H03K19/0185

Abstract: In an embodiment, a level shifter circuit for driving a load (HSP) via a power supply line (HVP) includes:
- an input stage (CL) for receiving an input signal (IN) switchable between a first and a second input level (0, LVP),
- an output stage (LL, A) coupled to the power supply line (HVP) to produce a drive signal (G) for the load (HSP), the output stage (LL, A) switchable between a first and a second output level (REF_HVP, HVP),
- a level translator (LT) set between the input stage (CL) and the output stage (LL, A), whereby the input signal (IN) switching between the first and second input levels (0, LVP) translates into the output stage (LL, A) switching between the first and second output levels (REF_HVP, HVP)-
A feedback element (10) is provided coupled to the output stage (LL, A) for transferring to the input stage (CL) a feedback signal (20) representative of the output level of the output stage (LL, A); the input stage (CL) includes control circuitry (12 to 18, 22) sensitive to the input signal (IN) and the feedback signal (Q_N) for detecting undesired switching of the output stage (LL, A) between the first and second output levels (REF_HVP, HVP) occurring in the absence of input signal (IN) switching between the first and second input levels (0, LVP), the control circuitry (12 to 22) being configured (22) for inverting the output level (Q_N) of the output stage (LL, A) resulting from undesired switching.

Abstract translation: 在一个实施例中，用于经由电源线（HVP）驱动负载（HSP）的电平移位器电路包括： - 输入级（CL），用于接收可在第一和第二输入电平 0，LVP）， - 耦合到电源线（HVP）以产生用于负载（HSP）的驱动信号（G）的输出级（LL，A），输出级（LL，A） 和第二输出电平（REF_HVP，HVP）， - 在输入级（CL）和输出级（LL，A）之间设置的电平转换器（LT），由此输入信号（IN）在第一和第二输入 电平（0，LVP）转换成在第一和第二输出电平（REF_HVP，HVP）之间切换的输出级（LL，A）。提供耦合到输出级（LL，A）的反馈元件（10） 将代表输出级（LL，A）的输出电平的反馈信号（20）提供给输入级（CL）; 输入级（CL）包括对输入信号（IN）和反馈信号（Q_N）敏感的控制电路（12至18,22），用于检测第一和第二输出之间的输出级（LL，A）的不希望的切换 在第一和第二输入电平（0，LVP）之间不存在输入信号（IN）切换的情况下发生的电平（REF_HVP，HVP），控制电路（12至22）被配置为用于将输出电平（Q_N ）由不希望的切换引起的输出级（LL，A）。

公开(公告)号：EP3025792A1

公开(公告)日：2016-06-01

申请号：EP15196387.3

申请日：2015-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： ROSSI, Sandro ,  GHISU, Davide Ugo ,  QUAGLIA, Fabio ,  LEONE, Antonio Davide

IPC: B06B1/02 ,  H03K3/64

CPC classification number: G05F3/02 ,  B06B1/0215 ,  H03K4/94 ,  H03K17/162

Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a current generator circuit (104), which generates current-integrator drive currents, a receiver (108), which amplifies transducer-echo signals, and control circuitry (102). The control circuitry generates one or more control signals to control generation of current-integrator drive currents by the current generator circuit during transducer-driving periods and reception of transducer-echo signals by the receiver during echo-reception periods. A current integrator (106) integrates current-integrator drive currents generated by current generator circuit to generate transducer drive signals.

Abstract translation: 传输通道传输高电压脉冲并接收高电压脉冲的回波。 传输通道包括产生电流积分器驱动电流的电流发生器电路（104），放大换能器回波信号的接收器（108）和控制电路（102）。 控制电路产生一个或多个控制信号，以在换能器驱动周期期间由电流发生器电路控制电流积分器驱动电流的产生，并且在回波接收周期期间由接收器接收换能器 - 回波信号。 电流积分器（106）集成由电流发生器电路产生的电流积分器驱动电流以产生换能器驱动信号。