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1.发明公开
公开(公告)号：EP1515431A1
公开(公告)日：2005-03-16
申请号：EP03425589.3
申请日：2003-09-11
Applicant: STMicroelectronics S.r.l.
Inventor： Gaeta, Marco , Bollati, Giacomino
CPC classification number: H03F3/45183 , H03F1/3211 , H03F3/45623 , H03G1/0088
Abstract: A step gain-variable CMOS amplifier is based on the basic structure of a differential amplifier including an input pair of transistors (M1,M2), a bias current generator (M11) connected between a common source node of the input pair of transistors and the ground node of the circuit and a pair of load transistors (M9,M10) of same type of conductivity of the input pair connected between the supply voltage node and, respectively, to the drain nodes of the input transistors. The novel structure according to this invention comprises a plurality of either the input pairs of transistors (M3,M4,M5,M6,M7,M8) or of load pairs of transistors connectable in parallel for increasing the effective width of the resultant transistors. A plurality of path selection pairs of switches may be programmably closed for connecting in parallel the selected pairs of either input transisitors or of load transistors.
Abstract translation: 步进增益CMOS放大器基于差分放大器的基本结构，该差分放大器包括输入一对晶体管（M1，M2），连接在输入晶体管对的公共源极之间的偏置电流发生器（M11）和 接地节点和连接在电源电压节点和输入晶体管的漏极节点之间的输入对具有相同类型导电性的一对负载晶体管（M9，M10）。 根据本发明的新颖结构包括多个晶体管（M3，M4，M5，M6，M7，M8）的输入对或者可并联连接的晶体管的负载对，以增加所得晶体管的有效宽度。 多个路径选择对开关可以可编程地闭合，用于并联连接所选择的输入通道或负载晶体管对。
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2.发明公开
公开(公告)号：EP1513252A1
公开(公告)日：2005-03-09
申请号：EP03425568.7
申请日：2003-09-02
Applicant: STMicroelectronics S.r.l.
Inventor： Gaeta, Marco , Bollati, Giacomino , Bongiorni, Marco
Abstract: In a logarithmic linear variable gain CMOS amplifier comprising a differential input pair of transistors with diode-connected load transistors, a second differential pair of transistors sharing the same diode-connected load transistors, a pair of current mirrors for programmably injecting respective bias currents in the common source modes of said two differential pairs of transistors, generated by a digital-to-analog converter, the groups delay is rendered independent from the gain and linearity inversely proportional to the gain by cross connnecting the control nodes of the second differential pair to the control nodes of the first differential input pair of transistors and by biasing the two differential pair of transistors such that the sum of their respecive bias current is maintained constant.
Preferably, transistor means connected in parallel to each of said diode-connected load transitors are added for subtracting a constant amount of current from said sum current that would otherwise be flowing through the diode-connected load transistors.Abstract translation: 在包括具有二极管连接的负载晶体管的差分输入对晶体管的对数线性可变增益CMOS放大器中，共享相同二极管连接的负载晶体管的第二差分对晶体管，一对电流镜，用于可编程地将相应的偏置电流注入到 由数模转换器产生的所述两个差分对晶体管的共模源，通过将第二差分对的控制节点与第二差分对的交叉连接相互连接，使组延迟独立于与增益成反比的增益和线性度 控制第一差分输入对晶体管的节点，并通过偏置两个差分对的晶体管，使得它们相应的偏置电流之和保持恒定。 添加并联连接到每个所述二极管连接的负载转换器的晶体管装置，用于从否则将流过二极管连接的负载晶体管的所述和电流中减去恒定量的电流。
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公开(公告)号：EP1515431B1
公开(公告)日：2008-09-24
申请号：EP03425589.3
申请日：2003-09-11
Applicant: STMicroelectronics S.r.l.
Inventor： Gaeta, Marco , Bollati, Giacomino
CPC classification number: H03F3/45183 , H03F1/3211 , H03F3/45623 , H03G1/0088
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