公开(公告)号：EP1435648A1

公开(公告)日：2004-07-07

申请号：EP02425807.1

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Moscatelli, Alessandro ,  Raffaglio, Claudia ,  Merlini, Alessandra ,  Galbiati, M. Paola

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66659 ,  H01L29/7835

Abstract: A process is disclosed for forming, on a common semiconductor substrate (S), CMOS transistors and vertical or lateral MOS transistors on at least first and second portions (A,C), respectively, of the substrate (S), the process comprising the following steps:

forming a first dielectric layer (14) on the whole substrate (S);
forming a first semiconductor material layer (15) on the first dielectric layer (14), in the first portion (A);
forming, on the whole substrate (S), a stack structure comprising a second dielectric layer (16), second semiconductor layer (17), and low-resistance layer (18); the process being in that it further comprises the steps of:

defining first ports (19) in the second semiconductor layer (17) and the low-resistance layer ( 18) to provide gate regions (20) of the vertical or lateral MOS transistors;
completely removing the second semiconductor layer (17) and the low-resistance layer (18) from the first portion (A) of the substrate (S) by using the second dielectric layer (16) as a screen;
defining second ports (22') in the second dielectric layer (16) and the second semiconductor layer (15) to provide gate regions (22) with the CMOS transistors;
screening off the gate region (20) of the vertical or lateral transistors with a protective layer (27);
forming a low-resistance layer (29) on the gate regions (22) of the CMOS transistors.

Abstract translation: 公开了一种用于在公共半导体衬底（S）上分别在衬底（S）的至少第一和第二部分（A，C）上形成CMOS晶体管和垂直或横向MOS晶体管的工艺，该工艺包括 以下步骤：在整个基板（S）上形成第一介电层（14）; 在第一部分（A）中在第一介电层（14）上形成第一半导体材料层（15）; 在整个基板（S）上形成包括第二介电层（16），第二半导体层（17）和低电阻层（18）的堆叠结构。 该方法还包括以下步骤：确定第二半导体层（17）和低电阻层（18）中的第一端口（19）以提供垂直或横向MOS晶体管的栅极区域（20）; 通过使用第二介电层（16）作为屏幕，从基板（S）的第一部分（A）完全去除第二半导体层（17）和低电阻层（18） 在第二介电层（16）和第二半导体层（15）中限定第二端口（22'），以向CMOS晶体管提供栅极区域（22）; 用保护层（27）屏蔽垂直或横向晶体管的栅极区域（20）; 在所述CMOS晶体管的栅极区域（22）上形成低电阻层（29）。