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    Low on-resistance LDMOS
    1.
    发明公开
    Low on-resistance LDMOS 审中-公开
    低导通电阻LDMOS

    公开(公告)号：EP1158583A1

    公开(公告)日：2001-11-28

    申请号：EP00830373.7

    申请日：2000-05-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Croce, Giuseppe ,  Moscatelli, Alessandro ,  Merlini, Alessandra ,  Galbiati, Paola

    IPC: H01L29/78 ,  H01L29/417

    CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456

    Abstract: An LDMOS structure is realized in a region of a first type of conductivity (N-POCKET) of a semiconductor substrate and comprises a gate, a drain region and a source region, the latter being constituted by a body diffusion (PBODY) of a second type of conductivity within said first region (N-POCKET), a source diffusion (N + ) of said first type of conductivity within said body diffusion (PBODY); an electrical connection diffusion (P + ) of said second type of conductivity, in a limited area of said source region, extending through said source diffusion (N + ) and reaching down to said body diffusion (PBODY), at least a source contact on said source diffusion (N + ) and said electrical connection diffusion (P + ), and further comprises a layer of silicide over the whole area of the source region short-circuiting said source diffusion (N + ) and said electrical connection diffusion (P + ); said source contact being established on said silicide layer.

    Abstract translation: LDMOS结构在半导体衬底的第一导电类型（N-POCKET）的区域中实现并且包括栅极，漏极区域和源极区域，后者由第二导电类型的体扩散（PBODY） 所述第一区域内的导电类型（N-POCKET），所述体扩散（PBODY）内所述第一导电类型的源极扩散（N +）; 在所述源极区域的有限区域中的所述第二类型导电性的电连接扩散（P +）延伸穿过所述源极扩散（N +）并到达所述体扩散（PBODY），所述源极上的至少源极接触 扩散（N +）和所述电连接扩散（P +），并且还包括在源区的整个区域上短路所述源扩散（N +）和所述电连接扩散（P +）的硅化物层; 所述源极触点建立在所述硅化物层上。

    Process of making CMOS and drain extension MOS transistors with silicided gate
    2.
    发明公开
    Process of making CMOS and drain extension MOS transistors with silicided gate 审中-公开
    Verfahren zur Herstellung von CMOS- und Drain-Extension MOS Transistoren mit silizidiertem Gate

    公开(公告)号：EP1435648A1

    公开(公告)日：2004-07-07

    申请号：EP02425807.1

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Moscatelli, Alessandro ,  Raffaglio, Claudia ,  Merlini, Alessandra ,  Galbiati, M. Paola

    IPC: H01L21/336

    CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66659 ,  H01L29/7835

    Abstract: A process is disclosed for forming, on a common semiconductor substrate (S), CMOS transistors and vertical or lateral MOS transistors on at least first and second portions (A,C), respectively, of the substrate (S), the process comprising the following steps:

    forming a first dielectric layer (14) on the whole substrate (S);
    forming a first semiconductor material layer (15) on the first dielectric layer (14), in the first portion (A);
    forming, on the whole substrate (S), a stack structure comprising a second dielectric layer (16), second semiconductor layer (17), and low-resistance layer (18); the process being in that it further comprises the steps of:

    defining first ports (19) in the second semiconductor layer (17) and the low-resistance layer ( 18) to provide gate regions (20) of the vertical or lateral MOS transistors;
    completely removing the second semiconductor layer (17) and the low-resistance layer (18) from the first portion (A) of the substrate (S) by using the second dielectric layer (16) as a screen;
    defining second ports (22') in the second dielectric layer (16) and the second semiconductor layer (15) to provide gate regions (22) with the CMOS transistors;
    screening off the gate region (20) of the vertical or lateral transistors with a protective layer (27);
    forming a low-resistance layer (29) on the gate regions (22) of the CMOS transistors.

    Abstract translation: 公开了一种用于在公共半导体衬底（S）上分别在衬底（S）的至少第一和第二部分（A，C）上形成CMOS晶体管和垂直或横向MOS晶体管的工艺，该工艺包括 以下步骤：在整个基板（S）上形成第一介电层（14）; 在第一部分（A）中在第一介电层（14）上形成第一半导体材料层（15）; 在整个基板（S）上形成包括第二介电层（16），第二半导体层（17）和低电阻层（18）的堆叠结构。 该方法还包括以下步骤：确定第二半导体层（17）和低电阻层（18）中的第一端口（19）以提供垂直或横向MOS晶体管的栅极区域（20）; 通过使用第二介电层（16）作为屏幕，从基板（S）的第一部分（A）完全去除第二半导体层（17）和低电阻层（18） 在第二介电层（16）和第二半导体层（15）中限定第二端口（22'），以向CMOS晶体管提供栅极区域（22）; 用保护层（27）屏蔽垂直或横向晶体管的栅极区域（20）; 在所述CMOS晶体管的栅极区域（22）上形成低电阻层（29）。

    RESURF LDMOS field-effect transistor
    3.
    发明公开
    RESURF LDMOS field-effect transistor 审中-公开
    RESURF-LDMOS-Feldeffekttransistor

    公开(公告)号：EP1148555A1

    公开(公告)日：2001-10-24

    申请号：EP00830308.3

    申请日：2000-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Croce, Giuseppe ,  Moscatelli, Alessandro ,  Merlini, Alessandra ,  Galbiati, Paola

    IPC: H01L29/78 ,  H01L29/36 ,  H01L29/08

    CPC classification number: H01L29/0878 ,  H01L29/7816

    Abstract: A RESURF LDMOS integrated structure realized in a first region (drain well) of a first type of conductivity defined in a semiconductor substrate of opposite type of conductivity and comprising a source region of said first type of conductivity formed in a body region of said opposite type of conductivity. Said body region is contained within a surface portion (body buffer region) of the first region that is more heavily doped than the rest of the region to avoid punch-through when the structure operates as a high side driver.

    Abstract translation: RESURF LDMOS集成结构，其实现于在相反导电类型的半导体衬底中限定的第一类型导电体的第一区域（漏极阱）中，并且包括形成在所述相反类型的体区域中的所述第一类型的导电源的源极区域 的电导率。 所述体区域包含在比其余区域更重掺杂的第一区域的表面部分（体缓冲区域）中，以避免当该结构作为高侧驱动器时起作用。

    Cascode power amplifier particularly for use in radiofrequency applications
    4.
    发明公开
    Cascode power amplifier particularly for use in radiofrequency applications 审中-公开
    Kaskoden-LeistungsverstärkerinsbesonderefürHF-Anwendungen

    公开(公告)号：EP1424771A1

    公开(公告)日：2004-06-02

    申请号：EP02425729.7

    申请日：2002-11-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Murari, Bruno ,  Moscatelli, Alessandro ,  Labate, Lorenzo

    IPC: H03F1/22

    CPC classification number: H03F1/223

    Abstract: A power amplifier comprising at least a load element (2) and at least an active element (3) inserted, in series to each other, between a first and a second voltage reference (Vdd, GND) is described.
    Advantageously, according to the invention, the load element (2) comprises a DMOS transistor (Ml).

    Abstract translation: 描述了功率放大器，其至少包括负载元件（2）和至少在第一和第二参考电压（Vdd，GND）之间彼此串联插入的有源元件（3）。 有利地，根据本发明，负载元件（2）包括DMOS晶体管（M1）。

    Method for manufacturing a MOS transistor and MOS transistor.
    5.
    发明公开
    Method for manufacturing a MOS transistor and MOS transistor. 审中-公开
    Verfahren zum Betreiben采用MOS晶体管

    公开(公告)号：EP1347511A1

    公开(公告)日：2003-09-24

    申请号：EP02425179.5

    申请日：2002-03-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Moscatelli, Alessandro ,  Croce, Giuseppe

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/823835 ,  H01L21/823857

    Abstract: A method for manufacturing a MOS transistor integrated into a chip (2) of semi-conductive material comprising a first (D-REG) and a second (S-REG) active region which extend from the inside of the chip to a surface (7) of the chip. The method comprises the steps of:

    a) forming a layer of insulating material (13) on the surface (7) of the chip (2) and deposition of a layer of conductive material (14) on said insulating layer,
    b) defining a insulated gate electrode (INS-G) of the transistor, starting from said superimposed insulating (13) and conductive (14) layers,
       characterized in that it also comprises the steps of:
    c) defining, starting from said superimposed insulating (13) and conductive (14) layers, an additional structure (ADD-STR) arranged on a first surface portion (N-well) of the first active region (D-REG),
    d) placing between the insulated gate electrode (INS-G) and the additional structure (ADD-STR) a dielectric spacer (C-SP) placed on a second surface portion (17) of the first active region (D-REG).

    Abstract translation: 一种集成到半导体材料芯片（2）中的MOS晶体管的制造方法，包括从芯片的内部延伸到表面（7）的第一（D-REG）和第二（S-REG）有源区 ）的芯片。 该方法包括以下步骤：a）在所述芯片（2）的表面（7）上形成绝缘材料层（13）并在所述绝缘层上淀积一层导电材料（14），b） 绝缘栅电极（INS-G），从所述重叠绝缘层（13）和导电层（14）开始，其特征在于还包括以下步骤：c）从所述重叠绝缘层（13）和 导电（14）层，布置在第一有源区（D-REG）的第一表面部分（N阱）上的附加结构（ADD-STR），d）放置在绝缘栅电极（INS-G）和 附加结构（ADD-STR）放置在第一有源区（D-REG）的第二表面部分（17）上的电介质间隔物（C-SP）。

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