公开(公告)号：EP1435648A1

公开(公告)日：2004-07-07

申请号：EP02425807.1

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Moscatelli, Alessandro ,  Raffaglio, Claudia ,  Merlini, Alessandra ,  Galbiati, M. Paola

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66659 ,  H01L29/7835

Abstract: A process is disclosed for forming, on a common semiconductor substrate (S), CMOS transistors and vertical or lateral MOS transistors on at least first and second portions (A,C), respectively, of the substrate (S), the process comprising the following steps:

forming a first dielectric layer (14) on the whole substrate (S);
forming a first semiconductor material layer (15) on the first dielectric layer (14), in the first portion (A);
forming, on the whole substrate (S), a stack structure comprising a second dielectric layer (16), second semiconductor layer (17), and low-resistance layer (18); the process being in that it further comprises the steps of:

defining first ports (19) in the second semiconductor layer (17) and the low-resistance layer ( 18) to provide gate regions (20) of the vertical or lateral MOS transistors;
completely removing the second semiconductor layer (17) and the low-resistance layer (18) from the first portion (A) of the substrate (S) by using the second dielectric layer (16) as a screen;
defining second ports (22') in the second dielectric layer (16) and the second semiconductor layer (15) to provide gate regions (22) with the CMOS transistors;
screening off the gate region (20) of the vertical or lateral transistors with a protective layer (27);
forming a low-resistance layer (29) on the gate regions (22) of the CMOS transistors.

Abstract translation: 公开了一种用于在公共半导体衬底（S）上分别在衬底（S）的至少第一和第二部分（A，C）上形成CMOS晶体管和垂直或横向MOS晶体管的工艺，该工艺包括 以下步骤：在整个基板（S）上形成第一介电层（14）; 在第一部分（A）中在第一介电层（14）上形成第一半导体材料层（15）; 在整个基板（S）上形成包括第二介电层（16），第二半导体层（17）和低电阻层（18）的堆叠结构。 该方法还包括以下步骤：确定第二半导体层（17）和低电阻层（18）中的第一端口（19）以提供垂直或横向MOS晶体管的栅极区域（20）; 通过使用第二介电层（16）作为屏幕，从基板（S）的第一部分（A）完全去除第二半导体层（17）和低电阻层（18） 在第二介电层（16）和第二半导体层（15）中限定第二端口（22'），以向CMOS晶体管提供栅极区域（22）; 用保护层（27）屏蔽垂直或横向晶体管的栅极区域（20）; 在所述CMOS晶体管的栅极区域（22）上形成低电阻层（29）。

公开(公告)号：EP1717850A1

公开(公告)日：2006-11-02

申请号：EP05425278.8

申请日：2005-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Moscatelli, Allesandro ,  Raffaglio, Claudia

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7835 ,  H01L29/402 ,  H01L29/66659

Abstract: Process for manufacturing a screened lateral power MOS transistor (D) on a same semiconductor substrate, the process comprising the following steps of:
forming, on at least a first weakly doped drain portion (3), a protective layer (11) of a first type of material,
forming, on said whole lateral MOS transistor (D), a dielectric layer (12) of a second type of material being selectively etchable with respect to said first type of material,
forming, in a single step, in said dielectric layer (12):
a first opening (13) to expose at least one portion of a highly doped source portion (5),
a second opening (15) to expose at least one portion of a highly doped drain portion (6),
at least a third opening (14) to expose at least one portion of said protective layer (11),
filling in said first, second and said at least third opening (13,15 and 14) by means of a conductive layer so as to form respective drain and source contacts (16,17) electrically connected to the first and second highly doped portions (5,6), and one electrical screen (18) substantially aligned with said protective layer (11).

Abstract translation: 在同一半导体衬底上制造屏蔽侧向功率MOS晶体管（D）的工艺，该方法包括以下步骤：在至少第一弱掺杂漏极部分（3）上形成第一 在所述整个横向MOS晶体管（D）上形成材料的类型，第二类型材料的电介质层（12）可相对于所述第一类型的材料选择性地蚀刻，在单个步骤中在所述电介质 层（12）：暴露高掺杂源极部分（5）的至少一部分的第一开口（13），第二开口（15），以暴露高度掺杂的漏极部分（6）的至少一部分， 至少第三开口（14）以暴露所述保护层（11）的至少一部分，通过导电层填充在所述第一，第二和所述至少第三开口（13,15和14）中以形成 电连接到第一和第二高掺杂p的相应的漏极和源极触点（16,17） （5,6）和与所述保护层（11）基本对准的一个电屏（18）。