公开(公告)号：EP1146545A1

公开(公告)日：2001-10-17

申请号：EP00830268.9

申请日：2000-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Pocorobba, Concetto ,  Grasso, Gianleonardo

IPC: H01L21/00

CPC classification number: H01L21/687

Abstract: A silicon wafer supporting device, for the evaporation of the wafer backside, comprising a plate-like element (10); its particularity consists of the fact that it comprises at least one blind seat (11) which is formed at the lower surface of the plate-like element (10) and is adapted to accommodate at least one silicon wafer (2) whose lower side must be subjected to a metallization process, a plurality of bracket-like elements (12) being rigidly fixed to the plate-like element (10) and being adapted to support the at least one silicon wafer (2) at its perimeter.

Abstract translation: 一种硅晶片支撑装置，用于晶片背面的蒸发，包括板状元件（10）; 其特殊性在于它包括至少一个盲板座（11），其形成在板状元件（10）的下表面处，并且适于容纳至少一个硅晶片（2），其中下侧必须 经受金属化处理，多个支架状元件（12）刚性地固定到板状元件（10）上并且适于在其周边支撑至少一个硅晶片（2）。

公开(公告)号：EP2927929A1

公开(公告)日：2015-10-07

申请号：EP15159971.9

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide Giuseppe ,  Grasso, Gianleonardo

IPC: H01J21/10 ,  G01K7/00

CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

Abstract: An integrated vacuum microelectronic structure (1) is described which includes:
a highly doped semiconductor substrate (11),
a first insulating layer (12) placed above the doped semiconductor substrate (11),
a first conductive layer placed above the first insulating layer,
a second insulating layer (93) placed above the first conductive layer,
a vacuum trench (19) formed within the first and second insulating layers (12, 93) and extending to the highly doped semiconductor substrate (11),
a second conductive layer (42) placed above the vacuum trench and acting as a cathode,
a third conductive layer (22) placed under the highly doped semiconductor substrate (11) and acting as an anode,
the second conductive layer (42) is placed adjacent to the upper edge (40) of the vacuum trench (19),
wherein the first conductive layer is separated from the vacuum trench (19) by portions of the second insulating layer and is in electrical contact with the second conductive layer (42). (Fig. 1).

公开(公告)号：EP2927929B1

公开(公告)日：2016-09-07

申请号：EP15159971.9

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide Giuseppe ,  Grasso, Gianleonardo

IPC: H01J21/10 ,  G01K7/00

CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

Abstract: An integrated vacuum microelectronic structure (1) is described which includes: a highly doped semiconductor substrate (11), a first insulating layer (12) placed above the doped semiconductor substrate (11), a first conductive layer placed above the first insulating layer, a second insulating layer (93) placed above the first conductive layer, a vacuum trench (19) formed within the first and second insulating layers (12, 93) and extending to the highly doped semiconductor substrate (11), a second conductive layer (42) placed above the vacuum trench and acting as a cathode, a third conductive layer (22) placed under the highly doped semiconductor substrate (11) and acting as an anode, the second conductive layer (42) is placed adjacent to the upper edge (40) of the vacuum trench (19), wherein the first conductive layer is separated from the vacuum trench (19) by portions of the second insulating layer and is in electrical contact with the second conductive layer (42). (Fig. 1).

Abstract translation: 描述了一种集成的真空微电子结构（1），其包括：高掺杂半导体衬底（11），置于掺杂半导体衬底（11）上方的第一绝缘层（12），置于第一绝缘层上方的第一导电层， 放置在第一导电层上方的第二绝缘层（93），形成在第一和第二绝缘层（12,93）内并延伸到高掺杂半导体衬底（11）的真空沟槽（19），第二导电层 42）放置在真空沟槽上方并用作阴极，第三导电层（22）放置在高度掺杂的半导体衬底（11）下并用作阳极，第二导电层（42）被放置成与上边缘 （40），其中所述第一导电层通过所述第二绝缘层的一部分与所述真空沟槽（19）分离，并且与所述第二导电层（42）电接触。 （图。1）。