中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.031 seconds)

    Insulated gate power semiconductor device with Schottky diode and manufacturing method thereof
    2.
    发明公开
    Insulated gate power semiconductor device with Schottky diode and manufacturing method thereof 有权
    Herstellungsverfahren eines Leistungs-Halbleiterbauelements mit isoliertem Gate und mit Schottky-Diode

    公开(公告)号：EP1420457A1

    公开(公告)日：2004-05-19

    申请号：EP02425695.0

    申请日：2002-11-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magri, Angelo ,  Frisina, Ferruccio

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66719 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/872

    Abstract: A process for integrating a Schottky contact to the drain inside the apertures of the elementary cells that constitute the integrated structure of an insulated gate power device in a totally self-alignment manner comprises the formation of a trench in said apertures by anisotropic etching using dielectric spacers. Therefore this process does not require a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages.
    A planar integrated insulated gate power device with high packing density of the elementary cells that compose it, having a Schottky diode electrically in parallel to the device, is also disclosed.
    In all devices the drain region under the Schottky contact is bounded by oppositely doped diffusion regions to shield electrical fields.
    A specific device includes an implanted buried region having a high resistivity located in the drain under the Schottky contact and at a greater depth than the trench.

    Abstract translation: 将肖特基接触集成到构成绝缘栅功率器件的全部自对准方式的集成结构的元件单元的孔内的漏极的工艺包括通过各向异性蚀刻在所述孔中形成沟槽，使用介质间隔物 。 因此，该过程不需要专门的掩蔽步骤。 这克服了增加集成功率器件的蜂窝结构的封装密度的可能性的限制，同时可以在器件的反极化下提高共同整合的肖特基二极管的性能并产生其它优点。 还公开了一种具有构成其的单元电池的高封装密度的平面集成绝缘栅功率器件，其具有与器件并联的肖特基二极管。 在所有器件中，肖特基接触下的漏极区域被相反掺杂的扩散区域限制，以屏蔽电场。 具体的器件包括位于肖特基接触之下的漏极中并具有比沟槽更深的深度的具有高电阻率的注入掩埋区。

    Process for manufacturing a high-scale-integration mos device
    4.
    发明公开
    Process for manufacturing a high-scale-integration mos device 审中-公开
    Prozess zur Herstellung eine hoch-integrierten MOS Bauelements。

    公开(公告)号：EP1780776A1

    公开(公告)日：2007-05-02

    申请号：EP05425762.1

    申请日：2005-10-28

    Applicant: STMicroelectronics S.r.l. ,  Lambda Physik AG ,  CONSIGLIO NAZIONALE DELLE RICERCHE

    Inventor： Simon, Frank ,  Magri, Angelo ,  Fortunato, Gugliemo ,  Privitera, Vittorio

    IPC: H01L21/268 ,  H01L29/78

    CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2683 ,  H01L21/324 ,  H01L29/49 ,  H01L29/6659

    Abstract: A process for manufacturing a MOS device (30) envisages the steps of: forming a gate structure (24) on a top surface (20a) of a semiconductor layer (20); forming a doped source/drain region (28) within a surface portion of the semiconductor layer (20) in a position adjacent to the gate structure (24); and irradiating the doped source/drain region (28) with an electromagnetic radiation (12a, 12b). The electromagnetic radiation (12a, 12b) is directed towards the top surface (20a) with a propagation direction having an incidence angle (+α,-α) non-zero with respect to the normal (n) to the top surface (20a). In particular, the electromagnetic radiation (12) is an excimer-laser radiation and comprises a first beam (12a) and a second beam (12b) having incidence angles (+α, -α) opposite to one another with respect to the normal (n).

    Abstract translation: 制造MOS器件（30）的工艺设想了以下步骤：在半导体层（20）的顶表面（20a）上形成栅极结构（24）; 在与所述栅极结构（24）相邻的位置中在所述半导体层（20）的表面部分内形成掺杂源极/漏极区（28）; 以及用电磁辐射（12a，12b）照射所述掺杂源极/漏极区域（28）。 电磁辐射（12a，12b）相对于顶表面（20a）的正常（n）的入射角（+±， - ±）非零的传播方向指向顶表面（20a） 。 特别地，电磁辐射（12）是准分子激光辐射，并且包括第一光束（12a）和第二光束（12b），其具有相对于法线（+ N）。

    Method of manufacturing a semiconductor power device
    5.
    发明公开
    Method of manufacturing a semiconductor power device 有权
    Herstellungsverfahren eines Leistungshalbleiterbauelements

    公开(公告)号：EP1742257A1

    公开(公告)日：2007-01-10

    申请号：EP05425483.4

    申请日：2005-07-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Arena, Giuseppe ,  Donato, Caterina ,  Camalleri, Cateno Marco ,  Magri, Angelo

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

    CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

    Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

    Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积具有小于第一介电材料层（9）的厚度的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在半导体本体（2）中，在栅极区域（14）的侧面和与栅极区域（14）绝缘的位置上形成有主体区域（7）和源极区域（8）。 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

Patent Agency Ranking