公开(公告)号：EP1217652B1

公开(公告)日：2003-09-24

申请号：EP00830834.8

申请日：2000-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Camalleri, Cateno Marco ,  Lorenti, Simona ,  Cali', Denise ,  Vasquez, Patrizia ,  Ferla, Giuseppe

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/66272 ,  H01L21/2256 ,  H01L29/7311

公开(公告)号：EP1217652A1

公开(公告)日：2002-06-26

申请号：EP00830834.8

申请日：2000-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Camalleri, Cateno Marco ,  Lorenti, Simona ,  Cali', Denise ,  Vasquez, Patrizia ,  Ferla, Giuseppe

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/66272 ,  H01L21/2256 ,  H01L29/7311

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon consists in carrying out, after having loaded the wafer inside the heated chamber of the reactorand evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally comprised between 500 and 1200°C and at a vacuum generally comprised between 0.1 Pa and 60000 Pa, and preferably at a temperature of 850°C ± 15°C and at a vacuum of 11000 Pa ± 2000 Pa, for a time generally comprised between 0.1 and 120 minutes, and most preferably between 0.5 and 1.5 minutes, in order to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux.
After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally comprised between 700 and 1000°C with nitrogen protoxide (N 2 O) for a time generally comprised between 0.1 and 120 minutes, preferably between 0.5 and 1.5 minutes.
The treatment with nitrogen protoxide (N 2 O) at such a vacuum and temperature conditions causes a relatively slow oxidation of the monocrystalline silicon and allows an effective control of the amount of oxygen at the interface and a great uniformity of distribution of it on the surface. The tunnel barrier characteristics in respect to the holes of the so created oxide film at the interface between the monocrystalline silicon and the polysilicon layer show an outstanding reproducibility.

Abstract translation: 在多晶硅和单晶硅之间的界面处控制键合氧原子的分布的数量和均匀性的方法包括在将晶片装入反应器的加热室内并在氮气下抽空LPCVD反应器的腔室 气氛中，在通常为500-1200℃的温度下，通常在0.1Pa和60000Pa之间的温度下，优选在850℃±15℃的温度下，用氢处理晶片， 真空度为11000Pa +/- 2000Pa，时间通常为0.1至120分钟，最优选为0.5至1.5分钟，以除去可能与表面上的硅组合的任何和全部氧 的单晶硅在反应器的加热室内加载期间即使在氮气通量下进行。 在这样的氢处理之后，基本上在相同的真空条件下和通常在700-1000℃的温度下用氮氧化丙烷（N 2 O）进行另外的处理，时间通常在0.1至120分钟之间，优选在0.5至 1.5分钟。 在这样的真空和温度条件下用氮氧化物（N 2 O）处理导致单晶硅的相对缓慢的氧化，并且允许有效地控制界面处的氧量并且在表面上具有很大的均匀分布。 相对于在单晶硅与多晶硅层之间的界面处所形成的氧化膜的孔的隧道势垒特性显示出突出的再现性。

公开(公告)号：EP1791173A1

公开(公告)日：2007-05-30

申请号：EP05425836.3

申请日：2005-11-25

Applicant: STMicroelectronics S.r.l. ,  Consiglio Nazionale delle Ricerche

Inventor： Salinas, Dario ,  Fortunato, Guglielmo ,  Magri',Angelo ,  Mariucci, Luigi ,  Cuscuna', Massimo ,  Camalleri, Cateno Marco

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/268 ,  H01L29/423 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/7802 ,  H01L21/268 ,  H01L21/28044 ,  H01L21/2815 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66712 ,  H01S5/0261

Abstract: A process for manufacturing a MOS device (40) envisages: providing a semiconductor layer (20); forming a gate structure (26) above the semiconductor layer (20); forming a first doped region (30; 45) within a first surface portion (20a) of the semiconductor layer (20); and irradiating the first doped region (30; 45) with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror (10) is formed above a second surface portion (20b) of the semiconductor layer (20). The dielectric mirror (10), in particular, of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from said electromagnetic radiation.

Abstract translation: 制造MOS器件（40）的工艺设想：提供半导体层（20）; 在所述半导体层（20）上形成栅极结构（26）; 在所述半导体层（20）的第一表面部分（20a）内形成第一掺杂区域（30; 45）; 并用电磁辐射照射第一掺杂区域（30; 45），进行退火。 在照射步骤之前，在半导体层（20）的第二表面部分（20b）的上方形成电介质镜（10）。 特别是布拉格反射器类型的电介质镜（10）至少部分地反映电磁辐射，并且保护下面的区域免受所述电磁辐射的影响。

公开(公告)号：EP1742257A1

公开(公告)日：2007-01-10

申请号：EP05425483.4

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Donato, Caterina ,  Camalleri, Cateno Marco ,  Magri, Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积具有小于第一介电材料层（9）的厚度的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在半导体本体（2）中，在栅极区域（14）的侧面和与栅极区域（14）绝缘的位置上形成有主体区域（7）和源极区域（8）。 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。