公开(公告)号：EP0929098A1

公开(公告)日：1999-07-14

申请号：EP98830006.7

申请日：1998-01-13

Applicant: STMicroelectronics S.r.l.

Inventor： Nicotra, Maria Concetta ,  Santangelo, Antonello ,  Masciarelli, Daniela Anna

IPC: H01L21/761 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76232

Abstract: A process for selectively introducing a dopant into the bottom of a trench (13) formed in a semiconductor material layer (10) provides for depositing a barrier layer (14) by means of a process of deposition over the semiconductor material layer (10), so as to form a deposited barrier layer (14) having, over lateral walls and a bottom wall of the trench, a thickness which is lower than a nominal thickness of the deposited barrier layer (14) over a planar surface of the semiconductor material layer (10), and implanting a dopant using the deposited barrier layer (14) as an implant mask.

Abstract translation: 的方法，用于选择性地将掺杂剂引入沟槽的底部（13）形成在半导体材料层（10）提供了一种通过沉积在半导体材料层的工艺来沉积阻挡层（14）（10） 以便形成具有沉积的阻挡层（14），用横向壁和沟槽的底壁的厚度的所有比在半导体材料层的平坦表面所沉积的阻挡层（14）的标称厚度下 （10），以及使用该沉积的阻挡层（14），以注入掩模注入的掺杂剂。