公开(公告)号：EP1024525A1

公开(公告)日：2000-08-02

申请号：EP99830037.0

申请日：1999-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello

IPC: H01L21/74 ,  H01L29/08 ,  H01L23/66

CPC classification number: H01L29/66272 ,  H01L29/41708 ,  H01L29/7322 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated power structure (100) for radio-frequency applications, formed in a chip of semiconductor material comprising, between a first (187) and a second (184) surface which are opposite each other, a substrate (103) on which at least one epitaxial layer (106, 112) is grown, the integrated structure (100) including at least one transistor (Tp) formed in an insulated portion (109, 142) of the chip and having a power terminal (E) located on the second surface (184), and at least one connection region (130, 136) in contact with the power terminal (E) and extending from the second surface (184) to the substrate (103) to electrically connect the power terminal (E) to the first surface (187), the at least one connection region (130, 136) comprising a groove (127) which extends from the second surface (184) to the substrate (103) and is filled with doped polysilicon (130).

Abstract translation: 在半导体材料芯片中形成的用于射频应用的集成功率结构（100）包括在彼此相对的第一（187）和第二（184）表面之间的衬底（103），衬底上至少有一个 外延层（106,112）生长，所述集成结构（100）包括形成在所述芯片的绝缘部分（109,142）中的至少一个晶体管（Tp），并且具有位于所述第二表面上的电源端子（E） （184），以及与所述电源端子（E）接触并从所述第二表面（184）延伸到所述基板（103）的至少一个连接区域（130,136），以将所述电源端子（E）电连接到所述电源端子 第一表面（187），所述至少一个连接区域（130,136）包括从第二表面（184）延伸到衬底（103）并且被掺杂多晶硅（130）填充的凹槽（127）。

公开(公告)号：EP1061572A1

公开(公告)日：2000-12-20

申请号：EP99830372.1

申请日：1999-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Lo Verde, Domenico ,  Santangelo, Antonello

IPC: H01L21/74 ,  H01L27/082 ,  H01L21/8222

CPC classification number: H01L29/66287 ,  H01L21/8222 ,  H01L27/0823

Abstract: Integrated structure (100) for radio frequency applications, formed in a chip of semiconductor material, comprising a substrate (103) having a first type of conductivity (P) on which at least one epitaxial layer (109, 118) is grown, at least one connecting region (106) having the first type of conductivity (P) extending from a free surface of the at least one epitaxial layer (109, 118) to the substrate (103), to form an insulating region which demarcates a portion of the at least one epitaxial layer (109, 118) in which a bipolar transistor (Tp) is formed, the transistor (Tp) comprising a collector region (115, 118, 127) having a second type of conductivity (N) delimited by the free surface and by the connecting region (106), a base region having the first type of conductivity (P) extending from the free surface into the collector region (115, 118, 127), and an emitter region having the second type of conductivity (N) extending from the free surface into the base region, in which are included conducting means (148, 157e) in contact on the free surface with one of the base region and the emitter region, and with the connecting region (106), to electrically connect the said one region to the substrate (103).

Abstract translation: 形成在半导体材料芯片中的用于射频应用的集成结构（100）包括至少一个外延层（109,118）生长至少具有第一类型导电性（P）的衬底（103） 具有从所述至少一个外延层（109,118）的自由表面延伸到所述基板（103）的第一类型的导电性（P）的一个连接区域（106），以形成绝缘区域 至少一个其中形成双极晶体管（Tp）的外延层（109,118），所述晶体管（Tp）包括具有第二导电类型（N）的集电极区域（115,118,127），所述第二导电类型（N）由所述自由 表面，并且通过连接区域（106），具有从自由表面延伸到集电区域（115,118,127）中的第一类型导电性（P）的基极区域和具有第二类型导电性的发射极区域 N）从自由表面延伸到基部区域中 在所述自由表面上与所述基极区域和所述发射极区域之一接触的导电装置（148,157e）以及所述连接区域（106）将所述一个区域电连接到所述基板（103）。

公开(公告)号：EP1635399A1

公开(公告)日：2006-03-15

申请号：EP04425671.7

申请日：2004-09-08

Applicant: STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello ,  Cascino, Salvatore ,  Gervasi, Leonardo

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/41

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659

Abstract: A lateral MOS device (1) is formed in a body (2) having a surface (7) and is formed by a semiconductor layer (40) of a first conductivity type; a drain region (10, 11) of a second conductivity type, formed in the semiconductor layer (40) and facing the surface (7); a source region (13) of the second conductivity type, formed in the semiconductor layer (40) and facing the surface (7); a channel (15) of the first conductivity type, formed in the semiconductor layer (40) between the drain region (10, 11) and the source region (13) and facing the surface (7); and an insulated gate region (20-22), formed on top of the surface (7) over the channel region (15). In order to improve the dynamic performance, a conductive region (23) extends only on one side of the insulated gate region (20-22), on top of the drain region (10, 11) but not on top of the insulated gate region.

Abstract translation: 横向MOS器件（1）形成在具有表面（7）的主体（2）中并且由第一导电类型的半导体层（40）形成; 形成在所述半导体层（40）中且面向所述表面（7）的第二导电类型的漏区（10,11）; 形成在所述半导体层（40）中并面向所述表面（7）的所述第二导电类型的源极区域（13）; 在所述漏极区域（10）和所述源极区域（13）之间的所述半导体层（40）中形成并面对所述表面（7）的第一导电类型的沟道（15）。 以及形成在通道区域（15）上方的表面（7）的顶部上的绝缘栅极区域（20-22）。 为了改善动态性能，导电区域（23）仅在绝缘栅极区域（20-22）的一侧上延伸，在漏极区域（10,11）的顶部上延伸，而不在绝缘栅极区域的顶部 。

公开(公告)号：EP0443296B1

公开(公告)日：1999-08-04

申请号：EP90830062.7

申请日：1990-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello ,  Magro, Carmelo ,  Lanza, Paolo

IPC: H01L21/285

CPC classification number: H01L21/28512

公开(公告)号：EP0749158B1

公开(公告)日：2001-10-31

申请号：EP95830249.9

申请日：1995-06-16

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello ,  Ferla, Giuseppe

IPC: H01L23/00 ,  H01L29/739 ,  H01L29/78 ,  H01L29/43 ,  H01L21/331

CPC classification number: H01L29/7802 ,  H01L29/49 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a metal film deposited on the polycrystalline silicon (4) and on the oxide layer (10).

公开(公告)号：EP1868247A1

公开(公告)日：2007-12-19

申请号：EP06425396.6

申请日：2006-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Cascino, Salvatore ,  Nicotra, Maria Concetta ,  Santangelo, Antonello

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66484 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

Abstract: MOS device (1) formed in a semiconductor body (2) having a first conductivity type and a surface (7) and housing a first current-conduction region (3) and a second current-conduction region (4), of a second conductivity type. The first and second current-conduction regions (3, 4) define between them a channel (5), arranged below a gate region (10), formed on top of the surface (7) and electrically insulated from the channel region (5). A conductive region (12) extends on top of a portion (5a) of the channel (5), adjacent to and insulated from the gate region only on a side thereof facing the first current-conduction region (3). The conductive region (12) is biased so as to modulate the current flowing in the channel (5).

Abstract translation: MOS器件（1）形成在具有第一导电类型的半导体本体（2）和表面（7）中，并且容纳第二导电区域（3）和第二电流传导区域（4） 类型。 第一和第二电流传导区域（3,4）在它们之间限定布置在栅极区域（10）下方的通道（5），形成在表面（7）的顶部上并且与沟道区域（5）电绝缘， 。 导电区域（12）在沟道（5）的一部分（5a）的顶部上延伸，仅在其面对第一电流传导区域（3）的一侧上与栅极区域相邻并与栅极区域绝缘。 导电区域（12）被偏置以便调制在通道（5）中流动的电流。

公开(公告)号：EP1017092A1

公开(公告)日：2000-07-05

申请号：EP98830797.1

申请日：1998-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello

IPC: H01L21/3205 ,  H01L21/266

CPC classification number: H01L28/20 ,  H01C17/003 ,  H01L21/266

Abstract: Process for manufacturing a resistive structure (1) comprising at least one semiconductor strip (2) laid above a semiconductor substrate (3) characterised in that it comprises the following steps of:

covering with a mask (4) said semiconductor strip (2);
forming a plurality of apertures (5) in said mask (4) until portions (6) of the semiconductor strip (2) are uncovered;
implanting dopant in said semiconductor strip (2) through said apertures (5);
subjecting the resistive structure (1) to a thermal process for diffusing the dopant in such a way to obtain a variable concentration profile in the semiconductor strip (2).

Abstract translation: 一种用于制造电阻结构（1）的方法，包括放置在半导体衬底（3）上方的至少一个半导体条（2），其特征在于包括以下步骤：用掩模（4）覆盖所述半导体条（2）; 在所述掩模（4）中形成多个孔（5），直到所述半导体条（2）的部分（6）未被覆盖; 通过所述孔（5）在所述半导体条（2）中注入掺杂剂; 使电阻结构（1）经受热处理以使掺杂剂扩散以获得半导体条（2）中的可变浓度分布。

公开(公告)号：EP0443297B1

公开(公告)日：1999-09-01

申请号：EP90830063.5

申请日：1990-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello ,  Magro, Carmelo ,  Ferla, Giuseppe ,  Lanza, Paolo

IPC: H01L21/285 ,  H01L21/60

CPC classification number: H01L29/66166 ,  H01L21/28518 ,  H01L21/76879

公开(公告)号：EP0929098A1

公开(公告)日：1999-07-14

申请号：EP98830006.7

申请日：1998-01-13

Applicant: STMicroelectronics S.r.l.

Inventor： Nicotra, Maria Concetta ,  Santangelo, Antonello ,  Masciarelli, Daniela Anna

IPC: H01L21/761 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76232

Abstract: A process for selectively introducing a dopant into the bottom of a trench (13) formed in a semiconductor material layer (10) provides for depositing a barrier layer (14) by means of a process of deposition over the semiconductor material layer (10), so as to form a deposited barrier layer (14) having, over lateral walls and a bottom wall of the trench, a thickness which is lower than a nominal thickness of the deposited barrier layer (14) over a planar surface of the semiconductor material layer (10), and implanting a dopant using the deposited barrier layer (14) as an implant mask.

Abstract translation: 的方法，用于选择性地将掺杂剂引入沟槽的底部（13）形成在半导体材料层（10）提供了一种通过沉积在半导体材料层的工艺来沉积阻挡层（14）（10） 以便形成具有沉积的阻挡层（14），用横向壁和沟槽的底壁的厚度的所有比在半导体材料层的平坦表面所沉积的阻挡层（14）的标称厚度下 （10），以及使用该沉积的阻挡层（14），以注入掩模注入的掺杂剂。