公开(公告)号：EP0881669B1

公开(公告)日：2005-12-14

申请号：EP97830259.4

申请日：1997-05-30

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Lombardo, Salvatore ,  Pinto, Angelo ,  Nicotra, Maria Concetta

IPC: H01L21/331

CPC classification number: H01L29/66242 ,  H01L21/26506

公开(公告)号：EP1868247A1

公开(公告)日：2007-12-19

申请号：EP06425396.6

申请日：2006-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Cascino, Salvatore ,  Nicotra, Maria Concetta ,  Santangelo, Antonello

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66484 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

Abstract: MOS device (1) formed in a semiconductor body (2) having a first conductivity type and a surface (7) and housing a first current-conduction region (3) and a second current-conduction region (4), of a second conductivity type. The first and second current-conduction regions (3, 4) define between them a channel (5), arranged below a gate region (10), formed on top of the surface (7) and electrically insulated from the channel region (5). A conductive region (12) extends on top of a portion (5a) of the channel (5), adjacent to and insulated from the gate region only on a side thereof facing the first current-conduction region (3). The conductive region (12) is biased so as to modulate the current flowing in the channel (5).

Abstract translation: MOS器件（1）形成在具有第一导电类型的半导体本体（2）和表面（7）中，并且容纳第二导电区域（3）和第二电流传导区域（4） 类型。 第一和第二电流传导区域（3,4）在它们之间限定布置在栅极区域（10）下方的通道（5），形成在表面（7）的顶部上并且与沟道区域（5）电绝缘， 。 导电区域（12）在沟道（5）的一部分（5a）的顶部上延伸，仅在其面对第一电流传导区域（3）的一侧上与栅极区域相邻并与栅极区域绝缘。 导电区域（12）被偏置以便调制在通道（5）中流动的电流。

公开(公告)号：EP0929098A1

公开(公告)日：1999-07-14

申请号：EP98830006.7

申请日：1998-01-13

Applicant: STMicroelectronics S.r.l.

Inventor： Nicotra, Maria Concetta ,  Santangelo, Antonello ,  Masciarelli, Daniela Anna

IPC: H01L21/761 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76232

Abstract: A process for selectively introducing a dopant into the bottom of a trench (13) formed in a semiconductor material layer (10) provides for depositing a barrier layer (14) by means of a process of deposition over the semiconductor material layer (10), so as to form a deposited barrier layer (14) having, over lateral walls and a bottom wall of the trench, a thickness which is lower than a nominal thickness of the deposited barrier layer (14) over a planar surface of the semiconductor material layer (10), and implanting a dopant using the deposited barrier layer (14) as an implant mask.

Abstract translation: 的方法，用于选择性地将掺杂剂引入沟槽的底部（13）形成在半导体材料层（10）提供了一种通过沉积在半导体材料层的工艺来沉积阻挡层（14）（10） 以便形成具有沉积的阻挡层（14），用横向壁和沟槽的底壁的厚度的所有比在半导体材料层的平坦表面所沉积的阻挡层（14）的标称厚度下 （10），以及使用该沉积的阻挡层（14），以注入掩模注入的掺杂剂。

公开(公告)号：EP0881669A1

公开(公告)日：1998-12-02

申请号：EP97830259.4

申请日：1997-05-30

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Lombardo, Salvatore ,  Pinto, Angelo ,  Nicotra, Maria Concetta

IPC: H01L21/331

CPC classification number: H01L29/66242 ,  H01L21/26506

Abstract: A process for fabricating a vertical structure high carrier mobility transistor on a substrate (1) of crystalline silicon doped with impurities of the N type, having a collector region (2) located at a lower portion of the substrate, the process comprising the steps of:

defining a window (10) in the semiconductor substrate (1);
providing a first implantation of germanium (Ge) atoms through said window (10);
providing a second implantation of acceptor dopants through said window (10) to define a base region;
applying an RTA treatment, or treatment in an oven, to reconstruct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy (Si 1-x Ge x );
forming a first thin dielectric layer (12) of silicon dioxide (SiO 2 ) by chemical vapor deposition; depositing a second dielectric layer (14) onto said first dielectric layer (12);
depositing a polysilicon layer (15) onto said second dielectric layer (14);
etching away, within the window region (10), said first (12) and second (14) dielectric layers, and the polysilicon layer (15), to expose the base region (3) and form isolation spacers (50) at the window edges;
forming an N-doped emitter (4) in the base (3) and window regions.

This fabrication process is specially attentive to the formation of the silicon dioxide SiO 2 /Ge x Si 1-x interface present in vertical structure HBT transistors, if isolation spacers are to be formed.
The fabrication process of this invention allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base currents from the ideal.

Abstract translation: 一种用于在掺杂有N型杂质的晶体硅的衬底（1）上制造垂直结构的高载流子迁移率晶体管的方法，其具有位于衬底下部的集电极区域（2），该方法包括以下步骤： ：在所述半导体衬底（1）中限定窗口（10）; 提供通过所述窗口（10）的锗（Ge）原子的第一注入; 提供通过所述窗口（10）的受体掺杂剂的第二注入以限定基极区域; 在烘箱中进行RTA处理或处理以重构包括硅/锗合金（Si1-xGex）的半导体衬底内的晶格; 通过化学气相沉积形成二氧化硅（SiO 2）的第一薄介电层（12）; 将第二介电层（14）沉积到所述第一介电层（12）上; 将多晶硅层（15）沉积到所述第二介电层（14）上; 在窗口区域（10），所述第一（12）和第二（14）电介质层和多晶硅层（15）之间蚀刻掉，以暴露基部区域（3）并在窗口处形成隔离间隔物（50） 边缘; 在基底（3）和窗口区域中形成N掺杂发射体（4）。 如果要形成隔离间隔物，则该制造工艺特别注意垂直结构HBT晶体管中存在的二氧化硅SiO 2 / G x Si 1-x界面的形成。 本发明的制造方法允许HBT晶体管的应用频率域进一步扩展，同时消除基极电流与理想电流的偏差。