公开(公告)号：EP1569242A1

公开(公告)日：2005-08-31

申请号：EP04425123.9

申请日：2004-02-27

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche, Mario ,  Di Martino, Alberto José ,  Signorello, Alfredo

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/24 ,  G11C16/16 ,  G11C16/34

Abstract: A memory device (10) formed by an array of memory cells (13) extending in rows and columns. The device is formed by a plurality of N-type wells (2) extending parallel to the rows; each N-type well (2) houses a plurality of P-type wells (3) extending in a direction transverse to the rows. A plurality of main bitlines (MBL) extend along the columns. Each P-type well is associated to a set of local bitlines (LBL) that extend along the respective P-type well and are connected to the drain terminals (D) of the cells accommodated in the respective P-type well. Local-bitlines managing circuits (14) are provided for each P-type well (3) and are arranged between the main bitlines (MBL) and a respective set of local bitlines (LBL) for controllably connecting each local bitline to a respective main bitline.

Abstract translation: 一种由行和列延伸的存储单元阵列形成的存储器件（10）。 该装置由平行于行延伸的多个N型阱（2）形成; 每个N型井（2）容纳在横向于行的方向上延伸的多个P型井（3）。 多个主位线（MBL）沿列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线（LBL）相关联，并连接到容纳在相应P型阱中的单元的漏极端子（D）。 为每个P型阱（3）提供局部位线管理电路（14），并且布置在主位线（MBL）和相应的一组本地位线（LBL）之间，用于将每个本地位线可控地连接到相应的主位线 。

公开(公告)号：EP2120124A1

公开(公告)日：2009-11-18

申请号：EP08425331.9

申请日：2008-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche, Mario ,  Grasso, Rosario Roberto

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: A circuit (10) is described for the generation of a temperature-compensated voltage reference (VBG) of the type comprising at least one generator circuit of a Band Gap voltage (13), inserted between a first and a second voltage reference (VDD, GND) and including an operational amplifier (OA1), having in turn a first and a second input terminal (T1, T2) connected to an input stage (15) connected to these first and second input terminal (T1, T2) and comprising at least one pair of a first and a second bipolar transistor (Q1, Q2) for the generation of a first voltage component (ΔVBE) proportional to the temperature.
Advantageously according to the invention, the circuit (10) comprises the control block (14) connected to the generator circuit of a Band Gap voltage (13) in correspondence with at least one first control node (Xc1) which is supplied with a biasing voltage value (VBase) comprising at least one voltage component which increases with the temperature for compensating the variations of the base-emitter voltage (Vbe) of the first and second bipolar transistors (Q1, Q2) and ensure the turn-on of a pair of input transistors of the operational amplifier (OA1). The circuit (10) has an output terminal (OUT) suitable for supplying a temperature-compensated voltage value (VBG) obtained by the sum of the first voltage component proportional to the temperature (ΔVBE) and of a second component inversely proportional to the temperature (VBE3).

Abstract translation: 一种电路（10）被描述为的类型包括带隙电压（13），第一和第二电压基准之间插入中的至少一个发生器电路的温度补偿的电压基准（VBG）的产生（VDD， GND）和包括（运算放大器（OA1），其具有依次在连接到论文的第一和第二输入端子（T1，T2输入级（15）连接到第一和第二输入端子T1，T2）），并在包含 为与温度成比例的第一电压分量（“VBE）的产生至少一对第一和第二双极晶体管（Q1，Q2）的。 有利的是雅丁到本发明，该电路（10）包括被提供有一个偏置电压连接到带隙电压（13）对应于至少一个第一控制节点（XC1）的发生器电路的控制模块（14）的所有 值（VBASE），其包含与所述温度增加用于补偿所述第一和第二双极晶体管（Q1，Q2）的基极 - 发射极电压（VBE）的变动的至少一个电压分量和确保接通一对的 所述运算放大器（OA1）的输入晶体管。 该电路（10）具有在输出端（OUT）适于提供由所述第一电压分量正比于温度（“VBE）的总和而得到的温度补偿的电压值（VBG）和第二组分的反比于 温度（VBE3）。