公开(公告)号：EP2320295A1

公开(公告)日：2011-05-11

申请号：EP10189487.1

申请日：2010-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Grasso, Rosario Roberto ,  Giaquinta, Maria

IPC: G05F3/30 ,  H03F3/393

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

Abstract: A bandgap voltage reference circuit ( 100 ) for generating a bandgap voltage reference ( Vbg ). Said circuit comprises a current generator ( 104 ) controlled by a first driving voltage ( Vpgate ) for generating a first current ( Iptat ) depending on the driving voltage, and a first reference circuit element ( 102 ) coupled to the controlled current generator ( 104 ) for receiving the first current and generating a first reference voltage ( Vpluse ) in response to the first current. The circuit further comprises a second reference circuit element ( 106 ) for receiving a second current ( Iptat ) corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage ( Vminuse ) in response to the second current. Said circuit further comprises a third reference circuit element ( 128 ) for receiving a third current ( Iptat ) corresponding to the first current and generating the bandgap reference voltage in response to the third current, and an operational amplifier ( 124 ). The operational amplifier has a first input terminal coupled to the first circuit element for receiving a first reference voltage input ( Vplus ) based on the first reference voltage, a second input terminal coupled to the second reference circuit element for receive a second input voltage ( Vminus ) based on the second reference voltage and an output terminal coupled to the controlled current generator to provide the first driving voltage ( Vpgate ) to the current generator according to the difference between the first input voltage and the second input voltage. The circuit also comprises a control circuit ( 134 ) comprising first capacitive means ( 136 ) and second capacitive means ( 138 ). The first capacitive means have a first terminal coupled to the first reference circuit element to receive the first reference voltage and a second terminal coupled to the first input terminal to provide the first input voltage. The second capacitive means comprise a first terminal coupled to the second reference circuit element for receiving the second reference voltage and a second terminal coupled to the second input terminal to provide the second input voltage. The control circuit also comprises biasing means ( 140 ) to selectively provide a common-mode voltage ( Vcm ) to the second terminals of the first and second capacitive means.

Abstract translation: 一种用于产生带隙电压基准（Vbg）的带隙电压参考电路（100）。 所述电路包括由第一驱动电压（Vpgate）控制的电流发生器（104），用于根据驱动电压产生第一电流（Iptat），以及耦合到受控电流发生器（104）的第一参考电路元件（102） 用于接收第一电流并响应于第一电流产生第一参考电压（Vpluse）。 电路还包括用于接收对应于第一电流的第二电流（Iptat）的第二参考电路元件（106） 所述第二参考电路元件适于响应于第二电流产生第二参考电压（Vminuse）。 所述电路还包括第三参考电路元件（128），用于接收对应于第一电流的第三电流（Iptat）并响应于第三电流产生带隙参考电压，以及运算放大器（124）。 运算放大器具有耦合到第一电路元件的第一输入端，用于基于第一参考电压接收第一参考电压输入（Vplus）;耦合到第二参考电路元件的第二输入端，用于接收第二输入电压（Vminus ）和耦合到受控电流发生器的输出端子，以根据第一输入电压和第二输入电压之间的差异向电流发生器提供第一驱动电压（Vpgate）。 电路还包括包括第一电容装置（136）和第二电容装置（138）的控制电路（134）。 第一电容装置具有耦合到第一参考电路元件以接收第一参考电压的第一端子和耦合到第一输入端子以提供第一输入电压的第二端子。 第二电容装置包括耦合到第二参考电路元件用于接收第二参考电压的第一端子和耦合到第二输入端子以提供第二输入电压的第二端子。 控制电路还包括偏置装置（140），以选择性地向第一和第二电容装置的第二端子提供共模电压（Vcm）。

公开(公告)号：EP2506434A1

公开(公告)日：2012-10-03

申请号：EP12162749.1

申请日：2012-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Ucciardello, Carmelo ,  Conte, Antonino ,  Matranga, Giovanni ,  Grasso, Rosario Roberto

IPC: H03K17/10 ,  H03K3/356

CPC classification number: H03K17/102 ,  H03K3/356113

Abstract: A biasing circuit (10; 10') has: an input designed to receive a supply voltage (Vi), a value of which is higher than a limit voltage (Vdd); a control stage (12; 12'), generating a first control signal (P gL ; N gL ) and a second control signal (P gR ; N gR ), with mutually complementary values, equal alternatively to a first value (Vi), in a first half-period of a clock signal, or to a second value (Vi - Vdd; Vi + Vdd), in a second half-period of the clock signal, the first and second values being a function of the supply voltage (Vi) and of the limit voltage (Vdd); and a biasing stage (16; 16'), which generates on an output a biasing voltage (V cp ; V cn ), as a function of the values of the first control signal (P gL ; N gL ) and of the second control signal (P gR ; N gR ). The first and second control signals are designed to control transfer transistors, for transferring the supply voltage (Vi) to respective outputs, whilst the biasing voltage is designed to control protection transistors in order to prevent overvoltages on the transfer transistors.

Abstract translation: 偏置电路（10; 10'）具有：设计成接收电压高于极限电压（Vdd）的电源电压（Vi）的输入端; 控制级（12; 12'），产生与第一值（Vi）相等的互补值的第一控制信号（P gL; N gL）和第二控制信号（P gR; N gR） 在时钟信号的第一半个周期中，或者在时钟信号的第二个半周期中为第二值（Vi-Vdd; Vi + Vdd），第一和第二值是电源电压的函数 Vi）和极限电压（Vdd）; 以及偏置级（16; 16'），其在输出上产生作为所述第一控制信号（P gL; N gL）和所述第二控制的值的函数的偏置电压（V cp; V cn） 信号（P gR; N gR）。 第一和第二控制信号被设计成控制传输晶体管，用于将电源电压（Vi）传送到相应的输出，同时偏置电压被设计成控制保护晶体管，以防止转移晶体管上的过电压。

公开(公告)号：EP2320296A1

公开(公告)日：2011-05-11

申请号：EP10189494.7

申请日：2010-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Giaquinta, Maria ,  Grasso, Rosario Roberto

IPC: G05F3/30 ,  H03F3/347

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

Abstract: A bandgap voltage reference circuit ( 100' ) for generating a bandgap reference voltage ( Vbg ) according to a first current ( Iptat ) is provided. Said circuit comprises a current generator ( 104 ) controlled by a first driving voltage ( Vpgate ) to generate the first current ( Iptat ) depending on the driving voltage. Said circuit further comprises a first reference circuit clement (102 ) adapted to generate a first reference voltage ( Vpluse ) based on the first current and a second reference circuit element ( 106 ) adapted to generate a second reference voltage ( Vminuse ) according to the first current. The circuit further comprises an operational amplifier ( 124' ) having a first input terminal coupled with the first circuit element for receiving a first reference input voltage ( Vplus ) based on the first reference voltage, a second input terminal coupled with the second reference circuit element for receiving a second input voltage ( Vminus ) based on the second reference voltage, and an output terminal coupled with the current generator to provide the first driving voltage. The circuit also comprises a control circuit ( 134 ). Said control circuit comprises first capacitive means ( 136 ) having a first terminal coupled with the first reference circuit element to receive the first reference voltage and a second terminal coupled with the first input terminal to provide the first input voltage. The control circuit further comprises second capacitive means ( 138 ) comprising a first terminal coupled with the second reference circuit element for receiving the second reference voltage and a second terminal coupled with the second input terminal to provide the second input voltage. The control circuit further comprises first biasing means ( 140' ) for selectively providing a first common-mode voltage ( Vcm ) to the second terminal of the first and second capacitive means. The operational amplifier is an offset compensated operational amplifier further comprising a first compensation terminal for receiving the first common-mode voltage and a second compensation terminal coupled with a compensation offset management circuit ( 600 ) for receiving a first compensation voltage ( Vc1 ). The offset management circuit comprises an auxiliary operational amplifier ( 902 ) having a first input terminal adapted to receive a third input voltage ( Vplus2 ) corresponding to the first input voltage, a second input terminal adapted to receive a fourth input voltage ( Vminus2 ) corresponding to the second input voltage and an output terminal adapted to be selectively coupled with a second compensation terminal of the operational amplifier for providing the first compensation voltage.

Abstract translation: 提供了用于根据第一电流（Iptat）产生带隙参考电压（Vbg）的带隙电压参考电路（100'）。 所述电路包括由第一驱动电压（Vpgate）控制的电流发生器（104），以根据驱动电压产生第一电流（Iptat）。 所述电路还包括适于基于第一电流产生第一参考电压（Vpluse）的第一参考电路元件（102）和适于根据第一电流产生第二参考电压（Vminuse）的第二参考电路元件（106） 当前。 电路还包括运算放大器（124'），其具有与第一电路元件耦合的第一输入端，用于基于第一参考电压接收第一参考输入电压（Vplus）;第二输入端与第二参考电路元件 用于接收基于第二参考电压的第二输入电压（Vminus）以及与电流发生器耦合的输出端以提供第一驱动电压。 电路还包括控制电路（134）。 所述控制电路包括具有与第一参考电路元件耦合以接收第一参考电压的第一端子的第一电容装置（136）和与第一输入端耦合以提供第一输入电压的第二端子。 控制电路还包括第二电容装置（138），包括与第二参考电路元件耦合以接收第二参考电压的第一端子和与第二输入端子耦合以提供第二输入电压的第二端子。 控制电路还包括用于选择性地向第一和第二电容装置的第二端提供第一共模电压（Vcm）的第一偏置装置（140'）。 所述运算放大器是还包括用于接收所述第一共模电压的第一补偿端子和与用于接收第一补偿电压（Vc1））的补偿偏移管理电路（600）耦合的第二补偿端的偏移补偿运算放大器。 偏移管理电路包括辅助运算放大器（902），其具有适于接收对应于第一输入电压的第三输入电压（Vplus2）的第一输入端子，适于接收与第一输入端相对应的第四输入电压（Vminus2）的第二输入端子 所述第二输入电压和输出端子适于与所述运算放大器的第二补偿端子选择性耦合，以提供所述第一补偿电压。

公开(公告)号：EP2120124A1

公开(公告)日：2009-11-18

申请号：EP08425331.9

申请日：2008-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche, Mario ,  Grasso, Rosario Roberto

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: A circuit (10) is described for the generation of a temperature-compensated voltage reference (VBG) of the type comprising at least one generator circuit of a Band Gap voltage (13), inserted between a first and a second voltage reference (VDD, GND) and including an operational amplifier (OA1), having in turn a first and a second input terminal (T1, T2) connected to an input stage (15) connected to these first and second input terminal (T1, T2) and comprising at least one pair of a first and a second bipolar transistor (Q1, Q2) for the generation of a first voltage component (ΔVBE) proportional to the temperature.
Advantageously according to the invention, the circuit (10) comprises the control block (14) connected to the generator circuit of a Band Gap voltage (13) in correspondence with at least one first control node (Xc1) which is supplied with a biasing voltage value (VBase) comprising at least one voltage component which increases with the temperature for compensating the variations of the base-emitter voltage (Vbe) of the first and second bipolar transistors (Q1, Q2) and ensure the turn-on of a pair of input transistors of the operational amplifier (OA1). The circuit (10) has an output terminal (OUT) suitable for supplying a temperature-compensated voltage value (VBG) obtained by the sum of the first voltage component proportional to the temperature (ΔVBE) and of a second component inversely proportional to the temperature (VBE3).

Abstract translation: 一种电路（10）被描述为的类型包括带隙电压（13），第一和第二电压基准之间插入中的至少一个发生器电路的温度补偿的电压基准（VBG）的产生（VDD， GND）和包括（运算放大器（OA1），其具有依次在连接到论文的第一和第二输入端子（T1，T2输入级（15）连接到第一和第二输入端子T1，T2）），并在包含 为与温度成比例的第一电压分量（“VBE）的产生至少一对第一和第二双极晶体管（Q1，Q2）的。 有利的是雅丁到本发明，该电路（10）包括被提供有一个偏置电压连接到带隙电压（13）对应于至少一个第一控制节点（XC1）的发生器电路的控制模块（14）的所有 值（VBASE），其包含与所述温度增加用于补偿所述第一和第二双极晶体管（Q1，Q2）的基极 - 发射极电压（VBE）的变动的至少一个电压分量和确保接通一对的 所述运算放大器（OA1）的输入晶体管。 该电路（10）具有在输出端（OUT）适于提供由所述第一电压分量正比于温度（“VBE）的总和而得到的温度补偿的电压值（VBG）和第二组分的反比于 温度（VBE3）。