公开(公告)号：EP2290697A1

公开(公告)日：2011-03-02

申请号：EP10174803.6

申请日：2010-09-01

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Magrí, Angelo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811

Abstract: A high voltage semiconductor device comprising a semiconductor substrate (2) covered by an epitaxial layer (3) of a first type of conductivity having a plurality of column structures (4) comprising high aspect ratio deep trenches, said epitaxial layer (3) being covered by an active surface area (5), each of the column structures (4) comprising an external portion (6) formed by a silicon epitaxial layer of a second type of conductivity, and having a dopant charge which counterbalances the dopant charge in said epitaxial layer (3) outside said column structures (4), a dielectric filling portion (7) filling up said deep trench, and said external portion (6) having a dopant concentration with a variable concentration profile having a maximum near an interface with said epitaxial layer (3).

Abstract translation: 一种高电压半导体器件，包括由第一导电类型的外延层（3）覆盖的半导体衬底（2），所述外延层具有包括高纵横比深沟槽的多个列结构（4），所述外延层（3）被覆盖 通过有源表面区域（5），每个列结构（4）包括由第二导电类型的硅外延层形成的外部部分（6），并且具有使所述外延层中的掺杂剂电荷平衡的掺杂剂电荷 在所述列结构（4）外部的层（3），填充所述深沟槽的介电填充部分（7），并且所述外部部分（6）具有可变浓度分布的掺杂浓度，所述掺杂浓度具有与所述外延 层（3）。

公开(公告)号：EP1873837A1

公开(公告)日：2008-01-02

申请号：EP06425448.5

申请日：2006-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Frisina, Ferruccio

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/739 ,  H01L29/872 ,  H01L29/732

CPC classification number: H01L29/7811 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a semiconductor power device envisages the steps of: providing a body (3) made of semiconductor material having a first top surface (3a); forming an active region (4a; 29, 30) with a first type of conductivity in the proximity of the first top surface (3a) and inside an active portion (1a) of the body (3); and forming an edge-termination structure (4b, 5). The edge-termination structure is formed by: a ring region (5) having the first type of conductivity and a first doping level, set within a peripheral edge portion (1b) of the body (3) and electrically connected to the active region; and a guard region (4b), having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface (3a) and connecting the active region (4a; 29, 30) to the ring region (5). The process further envisages the steps of: forming a surface layer (9) having the first type of conductivity on the first top surface (3a), also at the peripheral edge portion (1b), in contact with the guard region; and etching the surface layer (9) in order to remove it above the edge portion (1b) in such a manner that the etch terminates inside the guard region (4b).

Abstract translation: 一种用于制造半导体功率器件的工艺设想的以下步骤：提供由半导体材料制成的本体（3），其具有第一顶表面（3a）的; 形成于有源区（4a中; 29，30）与所述第一顶表面（3a）的附近的第一导电类型和内部向身体的活性部分（1a）中（3）; 和边缘终端结构的形成（图4b，5）。 边缘终端结构通过以下步骤形成：（5）具有第一导电类型和第一掺杂水平，外围边缘部分内设置一个环区（1b）的所述主体（3）和电连接到所述有源区; 和一个保护区（4b）的具有第一类型导电性的和第二掺杂水平，比所述第一掺杂水平较高，在所述第一顶表面（3a）的附近设置和连接所述有源区（4a中; 29，30 ）到环形区域（5）。 该方法进一步设想如下步骤：形成具有第一顶表面（3a）的所述第一导电类型的表面层（9），所以在周缘部分（1b）中，在与所述保护区接触; 并且为了蚀刻所述表面层（9），以寻求的方式没有蚀刻除去其边缘部分（1b）中上方的防护区域内终止（4b）中。