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    Built-in testing methodology in flash memory
    1.
    发明公开
    Built-in testing methodology in flash memory 有权
    Einbautes Testverfahren在einem Flash Speicher

    公开(公告)号：EP1453062A1

    公开(公告)日：2004-09-01

    申请号：EP03425126.4

    申请日：2003-02-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Kumar, Promod ,  Tomaiuolo, Francesko ,  Nicosia, Pierpaolo ,  De Ambroggi, Luca Giuseppe ,  Pipitone, Francesco

    IPC: G11C29/00

    CPC classification number: G11C29/16 ,  G11C16/04 ,  G11C2029/0401 ,  G11C2029/0405

    Abstract: An effective EWS flow is implemented by expanding the functions of the microcontroller normally embedded in a FLASH EPROM memory device and of the integrated test structures.
    The architecture gives the possibility of executing test routines internally without involving any external complex or expensive test equipment to control the test program. The algorithms are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE purposely provided). Such a GLOBAL CACHE may be downloaded with the desired routine to a TUI block and provides a full test flexibility also at the device debug level.
    Managing test routines by an internal algorithm permits to make the device architecture transparent from a tester point of view, by purposely creating a standard interface with a set of defined commands and instructions to be interpreted by the on board micro and internally executed.

    Abstract translation: 通过扩展通常嵌入在FLASH EPROM存储器件和集成测试结构中的微控制器的功能来实现有效的EWS流程。 该架构提供了在内部执行测试例程的可能性，而不涉及任何外部复杂或昂贵的测试设备来控制测试程序。 这些算法由板载微控制器执行（可能是从嵌入式ROM中读取或从有意提供的GLOBAL CACHE读取）。 这样的GLOBAL CACHE可以以期望的例程下载到TUI块，并且还可以在设备调试级别提供完整的测试灵活性。 通过内部算法管理测试例程允许从测试人员的角度使设备架构透明化，故意创建具有一组定义的命令和指令的标准接口，以由板上微内部执行 。

    A circuit for controlling a reference node in a sense amplifier
    3.
    发明公开
    A circuit for controlling a reference node in a sense amplifier 有权
    Lesaltstärkereert Referenzknotens in einemLeseverstärker

    公开(公告)号：EP1324347A1

    公开(公告)日：2003-07-02

    申请号：EP01830817.1

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Giove, Salvatore ,  De Ambroggi, Luca ,  Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Promod, Kumar ,  Piazza, Giuseppe ,  Pipitone, Francesco

    IPC: G11C16/28 ,  G11C7/06

    CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C16/28

    Abstract: A circuit (165) is proposed for controlling a reference node (Nr) in a sense amplifier (145) switchable between an operative condition and a stand-by condition, the reference node providing a reference voltage in the operative condition. The circuit includes means (Cp) for bringing the reference node to a starting voltage upon entry into the stand-by condition, first means (Rda1,Rda2) for keeping the reference node at a pre-charging voltage in the stand-by condition, second means (Rdb1,Rdb2) for providing a comparison voltage closer to the pre-charging voltage than the starting voltage, pulling means (Mu1) for pulling the reference node towards a power supply voltage, and control means (210) for activating the pulling means upon entry into the stand-by condition and for disabling the pulling means when the voltage at the reference node reaches the comparison voltage.

    Abstract translation: 提出了一种电路（165），用于控制在可操作状态和待机状态之间切换的读出放大器（145）中的参考节点（Nr），该参考节点在操作状态下提供参考电压。 电路包括用于在进入待机状态时使参考节点进入起始电压的装置（Cp），用于在备用状态下将参考节点保持在预充电电压的第一装置（Rda1，Rda2） 用于提供比起始电压更接近预充电电压的比较电压的第二装置（Rdb1，Rdb2），用于将参考节点拉向电源电压的牵引装置（Mu1），以及用于启动牵引 意味着当进入待机状态时，以及当参考节点处的电压达到比较电压时禁止拉动装置。

    Method and architecture for restricting access to a memory device
    4.
    发明公开
    Method and architecture for restricting access to a memory device 审中-公开
    一种用于限制对存储设备的访问的方法和体系结构

    公开(公告)号：EP1684152A1

    公开(公告)日：2006-07-26

    申请号：EP05100308.5

    申请日：2005-01-19

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Research & Development) Limited

    Inventor： Pipitone, Francesco ,  Tomaiuolo, Francesco ,  Messina, Marco ,  Raimondo, Alessandro ,  Malhi, Vijay

    IPC: G06F1/00 ,  G06F12/14

    CPC classification number: G06F12/1458 ,  G06F21/79

    Abstract: A memory device (102) including at least one storage area (108) for storing data and a protection control structure (234) adapted to selectively allow an external device (104) access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected. The memory device further includes a control logic (205,228) adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected. The memory device further includes means for providing a first code (RND) to the external device in said unlock procedure, means for receiving a second code from the external device in response to said first code, and means for verifying (240,229) validity of the received second code, wherein said means for verifying validity are adapted to ascertain a correspondence of the second code with the first code based on a predetermined relationship. Said control logic instructs the protection control structure to grant access to the storage area if the validity of the received second code has been verified.

    Abstract translation: 一种存储器装置（102），包括用于存储数据的至少一个存储区（108）和保护控制结构（234）angepasst以选择性地允许到外部设备（104）访问所述存储器的至少一个存储区域，所述存储 如果受保护的区域是通过外部设备不能随意访问。 所述存储器装置进一步包括控制逻辑（205.228）angepasst以识别由外部设备访问请求发送到所述至少一个存储区域，并用保护控制结构协作，用于管理解锁程序，用于选择性地授予外部装置至少临时访问 权限的存储区域，如果保护。 的所述存储器装置还包括用于在所述解锁过程中的外部装置提供一第一码（RND），用于响应从所述外部装置接收第二代码到所述第一代码，以及用于验证（240.229）的有效性 接收的第二代码，worin所述用于验证的有效性是angepasst以确定所述第二代码的一个对应于基于预定关系的第一个代码。 所述控制逻辑指示保护控制结构，如果所接收的第二代码的有效性已经被验证授予访问的存储区域。

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